Datasheet

Data Sheet AD9148
Rev. B | Page 29 of 72
Register Name
Addr
(Hex) Bit Name Function Default
PLL Control 2 0D 7:6 N2 REFCLK-to-PLL controller clock rate (f
PC_CLK
). 11
00 = 2.
01 = 4.
10 = 8.
11 = 16.
f
PC_CLK
must always be less than 50 MHz.
4
PLL cross
control enable
Enables PLL cross-point control.
3:2 N0 VCO-to-DACCLK divider. 001
00 = 1.
01 = 2.
10 = 4.
11 = 4.
1:0 N1 DACCLK-to-REFCLK divider. 01
00 = 2.
01 = 4.
10 = 8.
11 = 16.
PLL Status 0 0E 3:0 PLL control voltage PLL VCO control voltage readback value.
Read-
only
PLL Status 1 0F 5:0 VCO band readback VCO band value.
Read-
only
Sync Control 0 10 7 Sync enable Enables synchronization logic. 0
6
FIFO rate/data
rate toggle
Operates synchronization at the FIFO reset rate (0)/data rate (1). 0
3 Rising edge sync
Rising edge of CLK samples sync input (1), falling edge of
CLK samples sync input (0).
1
2:0 Sync averaging Average sync input of number of samples. 000
000 = 1.
001 = 2.
010 = 4.
011 = 8.
100 = 16.
101 = 32.
110 = 64.
111 = 128.