Datasheet

AD9148 Data Sheet
Rev. B | Page 28 of 72
Register Name
Addr
(Hex) Bit Name Function Default
Event Flag 0 (All bits
are high when interrupt
is active. Clear interrupt
by writing respective
bit high.)
06 7 PLL lock lost
1 = indicates that the PLL that was previously locked has
unlocked from the reference signal.
0
6 PLL lock
1 = indicates that the PLL has locked to the reference clock
input.
0
5 Sync lock lost
1 = indicates that the sync logic that was previously locked
has lost alignment.
0
4 Sync lock
1 = indicates that the sync logic achieved sync alignment. This
is indicated when no phase changes are requested for at least
a few full averaging cycles.
0
2 FIFO SPI aligned
1 = indicates that a FIFO reset originating from a serial port-
based request has successfully completed.
0
1 FIFO Warning 1
1 = indicates that the difference between the FIFO read and
write pointers is 1.
0
0 FIFO Warning 2
1 = indicates that the difference between the FIFO read and
write pointers is 2.
0
Event Flag 1(All bits are
high when interrupt is
active. Clear interrupt
by writing respective
bit high).
07 4 AED compare pass
1 = indicates that the SED logic detected a valid input data
pattern comparison against the preprogrammed expected
values.
0
3
AED compare fail
1 = indicates that the SED logic detected an invalid input data
pattern comparison against the preprogrammed expected
values. This automatically clears when eight valid I/Q data
pairs are received.
0
2 SED compare fail
1 = indicates that the SED logic detected an invalid input data
pattern comparison against the preprogrammed expected
values.
0
Clock Receiver Control 08 7
CLK duty
correction
Enables duty-cycle correction on CLK input. 0
6
REFCLK duty
correction
Enables duty-cycle correction on REFCLK input. 0
5
CLK cross
correction
Enables differential crossing correction on CLK input.
1
4
REFCLK cross
correction
Enables differential crossing correction on REFCLK input. 1
3:0 0111 Always set these bits to 0111 0111
PLL Control 0 0A 7 PLL enable Enables PLL clock multiplier. 0
6
PLL manual
enable
Enables PLL band selection mode (0 = auto, and 1 = manual). 1
5:0 Manual VCO band VCO band used in manual mode. 0
PLL Control 1 0C 7:5 PLL loop bandwidth Selects PLL loop filter bandwidth. 110
000 = narrowest bandwidth.
…
111 = widest bandwidth.
4:0 01001 Set these bits to 01001 for optimal PLL operation. 10001