Datasheet

AD9148 Data Sheet
Rev. B | Page 14 of 72
Pin No. Mnemonic Description
M7, L7 B6_P/B6_N LVDS Data Input Pair, Port B.
M8, L8 B7_P/B7_N LVDS Data Input Pair, Port B.
M9, L9 B8_P/B8_N LVDS Data Input Pair, Port B.
M10, L10 B9_P/B9_N LVDS Data Input Pair, Port B.
M11, L11
B10_P/B10_N
LVDS Data Input Pair, Port B.
K11, J11 B11_P/B11_N LVDS Data Input Pair, Port B.
M12, L12 B12_P/B12_N LVDS Data Input Pair, Port B.
K12, J12 B13_P/B13_N LVDS Data Input Pair, Port B.
M13, L13 B14_P/B14_N LVDS Data Input Pair, Port B.
M14, L14 B15_P/B15_N LVDS Data Input Pair, Port B (MSB).
K2, J2
DCIB_P/DCIB_N
LVDS Data Clock Input Pair for Port B.
K1, J1 FRAMEB_P/FRAMEB_N
LVDS Frame Input for Port B. Tie to LVDS logic low if not used.
Recommended external bias circuit is shown in Figure 49.