Datasheet

Data Sheet AD9148
Rev. B | Page 13 of 72
Pin No. Mnemonic Description
C14 IOUT4_N DAC 4 Complementary Output Current.
D14 IOUT4_P DAC 4 Positive Output Current.
C2 AUX1_N Auxiliary DAC 1 Complementary Output Current.
D2 AUX1_P Auxiliary DAC 1 Positive Output Current.
B3
AUX2_N
Auxiliary DAC 2 Complementary Output Current.
B4 AUX2_P Auxiliary DAC 2 Positive Output Current.
B11 AUX3_P Auxiliary DAC 3 Positive Output Current.
B12 AUX3_N Auxiliary DAC 3 Complementary Output Current.
C13 AUX4_N Auxiliary DAC 4 Complementary Output Current.
D13 AUX4_P Auxiliary DAC 4 Positive Output Current.
A8
I120
Tie to analog ground via a 10 kΩ resistor to generate a 120 µA reference current.
A7 VREF
Band Gap Voltage Reference I/O. Decouple to analog ground via a 0.1 µF
capacitor. Output impedance is approximately 5 kΩ.
B6, A6 CLK_P/CLK_N Positive/Negative DAC Clock Input (CLK).
B9, A9
REFCLK_P/REFCLK_N or
SYNC_P/SYNC_N
PLL Reference Clock Input (REFCLK_x). This pin has a secondary function as
a synchronization input (SYNC_x).
H4
IRQ Active Low Open-Drain Interrupt Request Output. Pull up to IOVDD with
a 10 kΩ resistor.
H3
RESET
An active low LVCMOS input resets the device. Pull up to IOVDD.
G1 SDO Serial Data Output for SPI.
G2
CS
Active Low Chip Select for SPI.
H1
SDIO
Serial Data Input/Output for SPI.
H2 SCLK Qualifying Clock Input for SPI.
G11, G12 TRENCH Connect this pin to VSS.
H12 PLL_LOCK Active High LVCMOS Output. It indicates the lock status of the PLL circuitry.
G13 TMS Reserved for Future Use. Connect to DVSS.
G14 TDI Reserved for Future Use. Connect to DVSS.
H13 TCK Reserved for Future Use. Connect to DVSS.
H14 TDO Reserved for Future Use. Leave unconnected.
M1, L1 A0_P/A0_N LVDS Data Input Pair, Port A (LSB).
P1, N1 A1_P/A1_N LVDS Data Input Pair, Port A.
M2, L2 A2_P/A2_N LVDS Data Input Pair, Port A.
P2, N2
A3_P/A3_N
LVDS Data Input Pair, Port A.
P3, N3 A4_P/A4_N LVDS Data Input Pair, Port A.
P4, N4 A5_P/A5_N LVDS Data Input Pair, Port A.
P5, N5 A6_P/A6_N LVDS Data Input Pair, Port A.
P6, N6 A7_P/A7_N LVDS Data Input Pair, Port A.
P7, N7 A8_P/A8_N LVDS Data Input Pair, Port A.
P8, N8
A9_P/A9_N
LVDS Data Input Pair, Port A.
P9, N9 A10_P/A10_N LVDS Data Input Pair, Port A.
P10, N10 A11_P/A11_N LVDS Data Input Pair, Port A.
P11, N11 A12_P/A12_N LVDS Data Input Pair, Port A.
P12, N12 A13_P/A13_N LVDS Data Input Pair, Port A.
P13, N13 A14_P/A14_N LVDS Data Input Pair, Port A.
P14, N14 A15_P/A15_N LVDS Data Input Pair, Port A (MSB).
K13, J13 DCIA_P/DCIA_N LVDS Data Clock Input Pair for Port A.
K14, J14 FRAMEA_P/FRAMEA_N
LVDS Frame Input for Port A. Tie to LVDS logic low if not used.
Recommended external bias circuit is shown in Figure 49.
K3, J3 B0_P/B0_N LVDS Data Input Pair, Port B (LSB).
M3, L3
B1_P/B1_N
LVDS Data Input Pair, Port B.
K4, J4 B2_P/B2_N LVDS Data Input Pair, Port B.
M4, L4 B3_P/B3_N LVDS Data Input Pair, Port B.
M5, L5 B4_P/B4_N LVDS Data Input Pair, Port B
M6, L6 B5_P/B5_N LVDS Data Input Pair, Port B.