Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) BGA 196

Quad 16-

Bit,1 GSPS,

TxDAC+ Digital-to-Analog Converter

Data Sheet

AD9148

Rev. B

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FEATURES

Single-carrier W-CDMA ACLR = 80 dBc at 150 MHz IF

Channel-to-channel isolation > 90 dB

Analog output

Adjustable 8.7 mA to 31.7 mA

= 25 Ω to 50 Ω

Novel 2×, 4×, and 8× interpolator eases data interface

On-chip fine complex NCO allows carrier placement

anywhere in DAC bandwidth

High performance, low noise PLL clock multiplier

Multiple chip synchronization interface

Programmable digital inverse sinc filter

Auxiliary DACs allow for offset control

Gain DACs allow for I and Q gain matching

Programmable I and Q phase compensation

Digital gain control

Flexible LVDS digital I/F supports 32- or 16-bit bus width

196-ball CSP_BGA, 12 mm × 12 mm

APPLICATIONS

Wireless infrastructure

LTE, TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM

MIMO/transmit diversity

Digital high or low IF synthesis

GENERAL DESCRIPTION

The AD9148 is a quad, 16-bit, high dynamic range, digital-to-

analog converter (DAC) that provides a sample rate of 1000 MSPS.

This device includes features optimized for direct conversion

transmit applications, including gain, phase, and offset compen-

sation. The DAC outputs are optimized to interface seamlessly with

analog quadrature modulators such as the ADL5371/ADL5372/

ADL5373/ADL5374/ADL5375. A serial peripheral interface (SPI)

is provided for programming of the internal device parameters.

Full-scale output current can be programmed over a range of 8.7 mA

to 31.7 mA. The device operates from 1.8 V and 3.3 V supplies

for a total power consumption of 3 W at the maximum sample

rate. The AD9148 is enclosed in a 196-ball chip scale package ball

grid array with the option of an attached heat spreader.

PRODUCT HIGHLIGHTS

1. Low noise and intermodulation distortion (IMD) enable

high quality synthesis of wideband signals from baseband

to high intermediate frequencies.

2. A proprietary DAC output switching technique enhances

dynamic performance.

3. The current outputs are easily configured for various

single-ended or differential circuit topologies.

4. The LVDS data input interface includes FIFO to ease input

timing.

TYPICAL SIGNAL CHAIN

FPGA/ASIC/DSP

NOTES

1. AQM = ANALOG QUADRATURE MODULATOR.

COMPLEX BASEBAND COMPLEX IF RF

LO ±

DAC1

DAC2

DIGITAL INTERPOLATION FILTERS

POST DAC

ANALOG FILTER

DAC3

DAC4

POST DAC

AQM

↑2 ↑2 ↑2

08910-001

Figure 1.

Summary of content (72 pages)

PAGE 1
Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter AD9148 Data Sheet FEATURES GENERAL DESCRIPTION Single-carrier W-CDMA ACLR = 80 dBc at 150 MHz IF Channel-to-channel isolation > 90 dB Analog output Adjustable 8.7 mA to 31.
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AD9148 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Synchronizing Multiple Devices .............................................. 45 Applications ....................................................................................... 1 Synchronization with Clock Multiplication ............................... 45 General Description .........................................................................
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Data Sheet AD9148 REVISION HISTORY 1/12—Rev. A to Rev. B Change to Chip ID Default Value, Table 12.................................25 Change to Chip ID Readback Value, Table 13.............................32 Changed 0x02 to 0x0A ...................................................................65 9/11—Rev. 0 to Rev. A Changes to General Description Section .......................................
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AD9148 Data Sheet FUNCTIONAL BLOCK DIAGRAM 310MHz 310MHz fS/2 SINC–1 MOD 310MHz/620MHz 2× I OFFSET I GAIN 2× 16-BIT DAC2 COS 32-BIT NCO SIN fS/2 AUX2 16-BIT DAC3 2× 2× FIFO I OFFSET I GAIN AUX3 2× fS/2 2× 2× 16-BIT DAC4 SINC–1 MOD AUX1_N IOUT2_P IOUT2_N AUX2_P AUX2_N IOUT3_P IOUT3_N GAIN Q OFFSET Q GAIN DCIB_P/ DCIB_N AUX1_P GAIN SINC–1 MOD 2× FRAMEB_P/ FRAMEB_N AUX1 2× SINC–1 MOD DATA RECEIVER AUX3_P AUX3_N IOUT4_P IOUT4_N HB3_EN HB3_CLK HB2_EN HB1_CLK HB2_CL
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Data Sheet AD9148 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Output Resistance Gain DAC Monotonicity Settling Time to Within ±0.
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AD9148 Data Sheet INPUT/OUTPUT SIGNAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL (SCLK, SDIO, CS, RESET, TMS, TDI, TCK) Input VIN Logic High (IOVDD = 1.8 V) Input VIN Logic High (IOVDD = 3.3 V) Input VIN Logic Low (IOVDD = 1.
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Data Sheet AD9148 DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3.
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AD9148 Data Sheet AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 5.
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Data Sheet AD9148 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD33, IOVDD DVDD18, CVDD18 AGND DGND CGND I120, VREF IOUT1_P, IOUT1_N, IOUT2_P, IOUT2_N, IOUT3_P, IOUT3_N, IOUT4_P, IOUT4_N A15_P to A0_P, A15_N to A0_N, B15_P to B0_P, B15_N, B0_N DCIA_P, DCIA_N, FRAMEA_P, FRAMEA_N, DCIB_P, DCIB_N, FRAMEB_P, FRAMEB_N CLK_P, CLK_N, REFCLK_P, REFCLK_N CSB, SCLK, SDIO, SDO, TDO, TDI, TCK, TMS, RESET, IRQ, PLL_LOCK Junction Temperature Storage Temperature Range Table 7.
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AD9148 Data Sheet Table 8. Thermal Resistance and Maximum Power Package Type 196-ball CSP_BGA 196-ball CSP_BGA 196-ball BGA_ED 196-ball BGA_ED 1 TA (°C) 85 85 85 85 PCB PCB Vias 25 25 25 25 PCB Layers 12 12 12 12 External Heat Sink1 No Yes No Yes Case CSP_BGA CSP_BGA BGA_ED BGA_ED TJ (°C) 125 125 125 125 θJA (°C/W) 18.0 16.0 15.0 14.0 Maximum Power (W) 2.22 2.50 2.67 2.86 Heat sink is used in the thermal model: 13 mm × 13 mm, 15 mm tall. Table 9. Power vs.
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Data Sheet AD9148 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 2 3 10 11 14 6 7 8 9 A IOUT2 IOUT2 CLK VREF I120 REF IOUT3 IOUT3 A B AUX2 CLK NC NC REF AUX3 B 1 5 4 AUX2 12 13 AUX3 C IOUT1 AUX1 AUX4 IOUT4 C D IOUT1 AUX1 AUX4 IOUT4 D E F X + + + + X X X X E X F G G H H J J K K L L M M N N P P + 3 CVDD18 4 X 5 AVDD33 6 7 AVSS 8 9 CLK 10 11 12 13 POSITIVE NEGATIVE TERMINAL CLK TERMINAL Figure 4.
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AD9148 Data Sheet 3 4 5 6 7 8 9 10 11 12 13 14 A A B B C C D D E E F F SPI INTERFACE G SDO CS + + Trch Trch TMS TDI G H SDIO SCLK RESET IRQ NC PLL TCK TDO H J FrB DCIB B0 B2 X X X X X X B11 B13 DCIA FrA J K FrB DCIB B0 B2 X X X X X X B11 B13 DCIA FrA K L A0 A2 B1 B3 B4 B5 B6 B7 B8 B9 B10 B12 B14 B15 L M A0 A2 B1 B3 B4 B5 B6 B7 B8 B9 B10 B12 B14 B15 M N A1 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
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Data Sheet AD9148 Pin No.
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AD9148 Pin No. M7, L7 M8, L8 M9, L9 M10, L10 M11, L11 K11, J11 M12, L12 K12, J12 M13, L13 M14, L14 K2, J2 K1, J1 Data Sheet Mnemonic B6_P/B6_N B7_P/B7_N B8_P/B8_N B9_P/B9_N B10_P/B10_N B11_P/B11_N B12_P/B12_N B13_P/B13_N B14_P/B14_N B15_P/B15_N DCIB_P/DCIB_N FRAMEB_P/FRAMEB_N Description LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B.
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Data Sheet AD9148 TYPICAL PERFORMANCE CHARACTERISTICS –30 –30 –40 –45 –45 –50 –55 –60 –65 –70 –55 –60 –65 –70 –75 –80 –80 –85 –85 100 150 200 250 300 fOUT (MHz) 08910-006 50 0 50 100 150 200 250 300 fOUT (MHz) Figure 6. Harmonic Level vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, Full-Scale Current = 20 mA 08910-009 –90 0 Figure 9. Highest Digital Spur vs.
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AD9148 Data Sheet –30 –30 –35 –45 –50 –55 –60 –65 –70 –75 –45 –50 –55 –60 –65 –70 –75 –80 –80 –85 –85 50 100 150 200 250 300 fOUT (MHz) 0 50 100 150 200 250 300 fOUT (MHz) Figure 12. Second Harmonic vs. fOUT over Digital Scale, Full-Scale Current = 20 mA, 4× Interpolation, fDATA = 150 MSPS 08910-015 –90 0 08910-012 –90 Figure 15. Third Harmonic vs.
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Data Sheet AD9148 –30 –30 –35 –35 –40 –40 –45 –45 –50 fDATA = 200MSPS fDATA = 310MSPS –50 fDATA = 150MSPS fDATA = 250MSPS –55 –60 IMD (dBc) –65 –70 –60 –65 –70 –75 –75 –80 –80 –85 –85 –90 –90 –95 –95 –100 150 200 250 300 350 fOUT (MHz) –100 0 –35 –40 –40 –45 –45 –50 –50 –55 –55 IMD (dBc) –60 fDATA = 125MSPS –80 –85 –85 –90 –90 –95 –95 –100 150 200 250 300 fOUT (MHz) 350 400 450 500 350 400 450 500 10mA 20mA 30mA –100 0 50 100 150 200 25
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AD9148 Data Sheet –144 –146 1×, 2×, 4×, 8×, –146 200MSPS 200MSPS 200MSPS 100MSPS –150 –152 –152 NSD (dBm/Hz) –150 –154 –156 –158 –162 –164 –164 50 100 150 200 250 fOUT (MHz) 300 350 400 –166 0 50 100 150 200 250 300 350 400 fOUT (MHz) Figure 27. Eight-Tone NSD Performance vs.
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Data Sheet AD9148 –50 –55 0dB, PLL ON 0dB, PLL OFF –3dB, PLL OFF –6dB, PLL OFF –60 ACLR (dBc) –65 –70 –75 –80 CENTER 150.00MHz #RES BW 30kHz VBW 300kHz –90 0 50 100 150 200 250 300 350 fOUT (MHz) 08910-030 RMS RESULTS –95 CARRIER POWER –13.47dBm/ 3.84000MHz Figure 30. One-Carrier W-CDMA ACLR vs. fOUT, Adjacent Channel, 4× Interpolation, fDATA = 184.32 MHz FREQ OFFSET 5.000MHz 10.00MHz 15.00MHz REF BW 3.840MHz 3.840MHz 3.840MHz SPAN 34.68MHz SWEEP 112.
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AD9148 Data Sheet CENTER 150.00MHz #RES BW 30kHz VBW 300kHz SPAN 59.58MHz SWEEP 193.2ms (601 PTS) 2 –19.29dBm 3 –19.24dBm 4 –19.61dBm FREQ OFFSET 5.000MHz 10.00MHz 15.00MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz LOWER dBc dBm UPPER dBc dBm –72.59 –91.81 –73.58 –92.81 –75.18 –94.40 –72.99 –92.22 –74.45 –93.67 –75.28 –94.51 START 1.0MHz #RES BW 30kHz Figure 36. Four-Carrier W-CDMA, fOUT = 150 MHz, fDAC = 737.28 MSPS, 4× Interpolation, −3 dBFS, PLL Off STOP 368.6MHz SWEEP 1.
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Data Sheet AD9148 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. In-Band Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate.
PAGE 22
AD9148 Data Sheet SERIAL PERIPHERAL INTERFACE DATA FORMAT SDO G1 SCLK G2 The instruction byte contains the information shown in Table 11. SPI PORT CS H2 Table 11. SPI Instruction Byte 08910-040 SDIO H1 I7 (MSB) R/W Figure 40. SPI Port The serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors.
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Data Sheet AD9148 SPI OPTIONS INSTRUCTION CYCLE The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by the LSB first bit (Register 0x00, Bit 6). The default is MSB first (LSB first = 0). The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first mode is active.
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AD9148 Data Sheet SPI REGISTER MAP Table 12.
PAGE 25
Data Sheet AD9148 0x21 Register Name Chip ID Coeff I Byte 0 Coeff I Byte 1 0x221 Coeff I Byte 2 0x231 Coeff I Byte 3 0 0x241 Coeff Q Byte 0 0 0x251 Coeff Q Byte 1 Coeff_3q[2:0] 0x261 Coeff Q Byte 2 Coeff_4q[2:0] 1 0x27 Coeff Q Byte 3 0x281 I phase adj LSB 0x291 I phase adj MSB Q phase adj LSB Q phase adj MSB I DC offset LSB Addr 0x1F 0x20 1 1 0x2A1 0x2B1 0x2C1 1 0x2D 0x2E1 0x2F1 IDAC FSC adj 0x311 IDAC control 0x321 AUX IDAC data 0x33 AUX IDAC control 0x341 QDAC FSC adj
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AD9148 Addr 0x54 0x55 0x56 0x57 0x58 0x59 0x5A Register Name FTW (LSB) FTW FTW FTW (MSB) Phase offset (MSB) Phase offset (LSB) DDS/mod control 0x5C Die Temp Control 0 0x5D Die Temp Control 1 Die temp LSB Die temp MSB DCI delay 0x5E 0x5F 0x72 1 Data Sheet Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FTW[7:0] FTW [15:8] FTW[23:16] FTW[31:24] NCO Phase Offset[15:8] Bit 2 Bit 1 Bit 0 Default 0x00 0x00 0x00 0x00 0x00 NCO Phase Offset[7:0] Bypass DDS/MOD Frame NCO reset ack 0 0 0 Frame NCO reset request FT
PAGE 27
Data Sheet AD9148 Register Name Addr (Hex) Bit Name Function Default Data Format 03 7 Binary format Input data is in twos complement format (0) or unsigned binary format (1). 0 6 Q first enable Indicates I/Q data pairing on data input; I first (0), Q first (1). 0 5 Dual-port mode Number of input data ports used. 1 Single port (0), dual port (1). 4 Bus swap 0 = normal data input bus pin out (MSB to LSB). 0 1 = inverted data input bus pin out (LSB to MSB).
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AD9148 Register Name Data Sheet Addr (Hex) 06 Event Flag 0 (All bits are high when interrupt is active. Clear interrupt by writing respective bit high.) Event Flag 1(All bits are high when interrupt is active. Clear interrupt by writing respective bit high). Clock Receiver Control PLL Control 0 PLL Control 1 07 08 0A 0C Bit Name Function Default 7 PLL lock lost 1 = indicates that the PLL that was previously locked has unlocked from the reference signal.
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Data Sheet AD9148 Register Name Addr (Hex) Bit Name Function Default PLL Control 2 0D 7:6 N2 REFCLK-to-PLL controller clock rate (fPC_CLK). 11 00 = 2. 01 = 4. 10 = 8. 11 = 16. fPC_CLK must always be less than 50 MHz. 4 PLL cross control enable Enables PLL cross-point control. 3:2 N0 VCO-to-DACCLK divider. 001 00 = 1. 01 = 2. 10 = 4. 11 = 4. 1:0 N1 DACCLK-to-REFCLK divider. 01 00 = 2. 01 = 4. 10 = 8. 11 = 16.
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AD9148 Data Sheet Register Name Addr (Hex) Bit Name Function Default Sync Control 1 11 5:0 Sync phase request Offset of internal divided by 64 clock phase after sync. 000000 000000 = 0 DAC clocks. … 111111 = 63 DAC clocks. Sync Status 0 Data Receiver Control 12 14 7 Sync Lost Synchronization lost. Readonly 6 Sync locked Synchronization found. Readonly 6 One DCI 0 = two DCIs used, DCIA_x and DCIB_x. 0 1 = one DCI used, DCIA_x.
PAGE 31
Data Sheet AD9148 Register Name Addr (Hex) Bit Name Function Default FIFO Status Port A 18 7:0 FIFO Level Thermometer encoded measure of the FIFO level. Readonly FIFO Status/ Control Port B 19 7 FIFO Warning 1 FIFO read and write pointers within ±1. Readonly 6 FIFO Warning 2 FIFO read and write pointers within ±2. Readonly 5 FIFO reset aligned FIFO read and write pointers aligned after chip reset.
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AD9148 Data Sheet Register Name Addr (Hex) HB2 Control 1D Bit Name Function Default HB2[2:0] Modulation mode for second stage interpolation filter (fHB2 = 2 × fIN2). 000 000 = input signal modulated by dc. Filter pass band is from −0.1 to +0.1 of fHB2. 001 = input signal modulated by dc. Filter pass band is from 0.025 to 0.225 of fHB2. 010 = input signal modulated by fHB2/4. Filter pass band is from 0.15 to 0.35 of fHB2. 011 = input signal modulated by fHB2/4. Filter pass band is from 0.
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Data Sheet AD9148 Register Name Addr (Hex) Bit Name Function Default Coeff I Byte 0 20 7 0 Set this bit to 0. 0 6:3 Coeff_1i[3:0] I-Path DAC Sinc-1 Filter Coefficient 2 in twos complement format. 0 2:0 Coeff_0i I-Path DAC Sinc-1 Filter Coefficient 1 in twos complement format. 0 Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Coeff I Byte 1 21 7:5 Coeff_3i[2:0] I-Path DAC Sinc-1 Filter Coefficient 4 (LSB) in twos complement format.
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AD9148 Data Sheet Register Name Addr (Hex) Bit Name Function Default Coeff Q Byte 2 26 7:5 Coeff_4q[2:0] Q-Path DAC Sinc-1 Filter Coefficient 5 (LSB) in twos complement format. 0 4 0 Set this bit to 0. 0 3:0 Coeff_3q[6:3] Q-Path DAC Sinc Filter Coefficient 4 (MSB) in twos complement format. -1 D Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Coeff Q Byte 3 27 7 0 Set this bit to 0.
PAGE 35
Data Sheet AD9148 Register Name Addr (Hex) Bit Name Function IDAC FSC Adj 30 7:0 IDAC FSC Adj IDAC full-scale current adjustment (LSB part). IDAC FS Adj[9:0] F9 sets the full-scale current of the IDAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 µA. Default 0x000 = 8.64 mA. ... 0x200 = 20.14 mA. … 0x3FF = 31.66 mA. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path.
PAGE 36
AD9148 Data Sheet Register Name Addr (Hex) Bit Name Function QDAC FSC Adj 34 7:0 QDAC FSC Adj F9 Q DAC full-scale current adjustment (LSB part). QDAC FS Adj[9:0] sets the full-scale current of the QDAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 µA. Default 0x000 = 8.64 mA ... 0x200 = 20.14mA … 0x3FF = 31.66 mA Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path.
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Data Sheet AD9148 Register Name Addr (Hex) Bit Name SED_S0_L 38 7:0 SED Compare Compare Pattern Sample0[15:0] is the word that is compared Pattern Sample0[7:0] with Data Sample 0 captured at the input interface by the rising edge of DCI. Function Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B.
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AD9148 Data Sheet Register Name Addr (Hex) Bit Name SED Control/Status 40 7 SED compare enable Enables the SED circuitry. 6 Port B error detected Status of last compare on Port B. 0 5 Port A error detected Status of last compare on Port A. 0 3 Auto-clear enable Enables the auto reset after eight valid sample sets. 0 2 Port B compare failed Fail status determined for last sample set on Port B. 0 1 Port A compare failed Fail status determined for last sample set on Port A.
PAGE 39
Data Sheet AD9148 Register Name Addr (Hex) Bit Name Function Default FTW (LSB) 54 7:0 FTW[7:0] See Register 0x57. 0 FTW 55 7:0 FTW[15:8] See Register 0x57. 0 FTW 56 7:0 FTW [23:16] See Register 0x57. 0 FTW (MSB) 57 7:0 FTW [31:24] FTW[31:0] is the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written.
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AD9148 Data Sheet INPUT DATA PORTS DUAL-PORT MODE In dual-port mode, the DCI signal indicates to which DAC the data is intended. On the rising edge of DCI, data is latched into DAC 1 and DAC 3. On the falling edge of DCI, data is latched into DAC 2 and DAC 4. This pattern repeats continuously. There is a SPI programmable option (Register 0x14[6]) to provide one DCI for both input ports or two DCIs, where each DCI is associated with one input port.
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Data Sheet AD9148 BYTE MODE In byte mode, a FRAME signal must be provided along with the DCI signal and the data. The most significant byte of the data should correspond with DCI being high, and the least significant byte of the data should correspond with DCI being low. The FRAME signal indicates to which DAC the data is intended. When FRAME is high, data on the top half of the port (A[15:8]) is sent to DAC 1 and data on the bottom half of the port (A[7:0]) is sent to DAC 3.
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AD9148 Data Sheet FIFO OPERATION 32 BITS REG 0 REG 1 32 DATA PORT A INPUT LATCH REG 2 DATA ASSEMBLER REG 3 32 DATA PATHS 32 REG 4 DAC1 AND DAC2 REG 5 REG 6 32 REG 7 WRITE PTR A WRITE PTR RESET LOGIC FIFO A OFS[2:0] FRAMEA READ PTR RESET FIFO RATE/ WRITE PTR RESET 32 BITS WRITE PTR B DCIB ONE DCI READ POINTER B SYNC LOGIC FRAMEB REG 0 REG 1 REG 2 DATA PORT B INPUT LATCH DACCLK ÷INT FIFO B OFS[2:0] DATA RATE READ POINTER A DCIA DATA ASSEMBLER 32 REG 3 REG 4 32 DATA PATHS
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Data Sheet AD9148 To avoid any concurrent reads and writes to the same FIFO address and to assure a fixed pipeline delay, it is important to reset the state of the FIFO pointers to known states. The pipeline delay in the AD9148 comes from two sources, FIFO delay and the delay though the signal processing in the DAC.
PAGE 44
AD9148 Data Sheet No Synchronization 3. In this mode, Bit 7 in Register 0x10 is set to 0, the pipeline delay in the signal processing is not controlled, and the read pointer of the FIFO is never reset. However, to assure that the FIFO can operate safely and there is no concurrent access to FIFO from the write and read pointer to the same address, it is important to ensure that the phase offset between the two pointers is greater than 2.
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Data Sheet AD9148 DEVICE SYNCHRONIZATION SYNCHRONIZING MULTIPLE DEVICES System demands may require that the outputs of multiple DACs be synchronized with each other or with a system clock. Systems that support transmit diversity or beam-forming, where multiple antennas are used to transmit a correlated signal, require multiple DAC outputs to be phase aligned with each other.
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AD9148 Data Sheet The following procedure outlines the steps required to synchronize multiple devices. The procedure assumes that the REFCLK/SYNC signal is applied to all of the devices and the PLL of each device is phase locked to it. Each individual device must follow this procedure. The procedure for synchronization when using the PLL follows: 2. 3. Configure for data rate, periodic synchronization by writing 0xC0 to the sync control register (Register 0x10).
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Data Sheet AD9148 LOW SKEW CLOCK DRIVER CLK REFCLK/SYNC OUT1 FRAME SAMPLE RATE CLOCK DCI LOW SKEW CLOCK DRIVER MATCHED LENGTH TRACES CLK REFCLK/SYNC OUT2 FRAME SYNC CLOCK DCI MATCHED LENGTH TRACES 08910-054 FPGA Figure 55. Typical Circuit Diagram for Synchronizing Devices to a System Clock SYNCHRONIZATION WITH DIRECT CLOCKING When directly sourcing the DAC sample rate clock to CLK, a separate REFCLK/SYNC input signal is required for synchronization.
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AD9148 Data Sheet Generally, for values of N equal to or greater than 3, the FIFO rate synchronization mode is chosen. The following procedure outlines the steps required to synchronize multiple devices in FIFO rate mode. The procedure assumes that the CLK and REFCLK/SYNC signals are applied to all of the devices. Each individual device must follow the procedure. Figure 57 shows the synchronization signal timing with 2× interpolation, so that fDCI = ½ × fCLK.
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Data Sheet AD9148 INTERFACE TIMING DACCLK/ REFCLK SAMPLING INTERVAL DCI The setup (tS) and hold (tH) times with respect to the edges are shown in Figure 59. The minimum setup and hold times are shown in Table 16. Table 16. Data Port Setup and Hold Times DCI Delay (Register 0x72, Bits[1:0]) 00 01 10 11 Minimum Setup Time, tS (ns) −0.02 −0.16 −0.28 −0.36 tDATA tSDCI 08910-057 The timing diagram for the digital interface port is shown in Figure 59.
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AD9148 Data Sheet DIGITAL DATA PATH The block diagram in Figure 60 shows the functionality of the complex digital data path. The digital processing includes a premodulation block, a programmable complex filter, three half-band interpolation filters with built-in coarse modulation, a quadrature modulator with a fine resolution NCO as well as phase, gain, and offset adjustment blocks.
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Data Sheet AD9148 Table 18.
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AD9148 Data Sheet Half-Band Filter 1 (HB1) 0.02 HB1 has four modes of operation, as shown in Figure 64. The shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors: the filter center frequency and whether the filter modulates the input signal. MODE 2 MODE 1 MAGNITUDE (dB) MODE 0 0 MODE 3 0 –0.02 –0.04 –0.06 –0.08 –40 –0.10 0 08910-064 MAGNITUDE (dB) –20 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 –60 (× fIN1) Figure 65.
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Data Sheet AD9148 MODE 1 MODE 3 0.02 MODE 5 MODE 7 0 0 MAGNITUDE (dB) –40 –60 –80 –0.02 –0.04 –0.06 –0.08 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 (× fIN2) 1.8 2.0 –0.10 08910-066 –100 0 0.12 0.16 0.20 0.24 0.28 0.32 Figure 68. Pass-Band Detail of HB2 As shown in Figure 66 and Figure 67, the center frequency in each mode is offset by ¼ of the input data rate (fIN2) of the filter. Mode 0 through Mode 3 do not modulate the input signal.
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AD9148 Data Sheet 0.02 0 ×2 MODE ×4 MODE ×8 MODE 0.4 COMPLEX BW (×fDAC) Figure 69 shows the pass-band filter response for HB3. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 24 shows the pass-band flatness and stop-band rejection the HB3 filter supports at different bandwidths. 0.3 0.2 0.15 0.1 0.075 –0.
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Data Sheet AD9148 The frequency tuning word registers are not updated immediately upon writing as the other configuration registers do. After loading the FTW registers with the desired values, Bit 2 of Register 0x5A must transition from 0 to 1 for the new FTW to take effect. Phase Offset Adjustment A 16-bit phase offset may be added to the output of the phase accumulator via the serial port.
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AD9148 Data Sheet CLOCK GENERATION DAC INPUT CLOCK CONFIGURATIONS DRIVING THE CLK_x AND REFCLK_x INPUTS The AD9148 DAC sample clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying employs the on-chip, phased-locked loop (PLL) that accepts a reference clock (REFCLK_x) operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency.
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Data Sheet AD9148 0x06[7:6] PLL LOCK PLL LOCK LOST REFCLK_P/REFCLK_N (PIN B9 AND PIN A9) 0x0D[7:6] N2 PC_CLK LOOP FILTER VCO ÷N1 ÷N0 0x0D[1:0] N1 0x0D[3:2] N0 DACCLK CLK_P/CLK_N (PIN B6 AND PIN A6) 08910-072 ÷N2 PHASE DETECTION 0x0E[3:0] PLL CONTROL VOLTAGE ADC 0x0A[7] PLL ENABLE Figure 74. PLL Clock Multiplication Circuit Table 25.
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AD9148 Data Sheet Manual VCO Band Select Table 26. VCO Control Voltage Range Indications The device also has a manual band select mode that allows the user to select the VCO tuning band. When in manual mode (enabled by setting Bit 6, Register 0x0A to 1), the VCO band is set directly with the value written to the manual VCO band bit enabled (Bits[5:0], Register 0x0A). To properly select the VCO band, complete the following sequence: VCO Control Voltage 1111 1110 1101 1. 2. 3. 4.
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Data Sheet AD9148 ANALOG OUTPUTS For nominal values of VREF (1.2 V), RSET (10 kΩ), and DAC gain (512), the full-scale current of the DAC is typically 20.16 mA. The DAC full-scale current can be adjusted from 8.66 mA to 31.66 mA by setting the DAC gain parameter setting as shown in Figure 76. TRANSMIT DAC OPERATION Figure 77 shows a simplified block diagram of one pair of the transmit path DACs.
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AD9148 Data Sheet Transmit DAC Output Configurations Transmit DAC Linear Output Signal Swing The optimum noise and distortion performance of the AD9148 is realized when it is configured for differential operation. The common-mode error sources of the DAC outputs are reduced significantly by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise.
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Data Sheet AD9148 Baseband Filter Implementation In addition, the P or N output can act as a current source or a current sink. When sourcing current, the output compliance voltage is 0 V to 1.6 V. When sinking current, the output compliance voltage is 0.8 V to 1.6 V. The auxiliary DAC current direction is programmable via Bit 6, Register 0x33 and Bit 6, Register 0x37 (DAC SPI select is 0 to control AUX1 and AUX2, and DAC SPI select is 1 to control AUX3 and AUX4).
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AD9148 Data Sheet Reducing LO Leakage and Unwanted Sidebands Analog Devices modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output.
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Data Sheet AD9148 DEVICE POWER DISSIPATION The AD9148 has four supply rails: AVDD33, IOVDD, DVDD18, and CVDD18. 3.25 3.00 POWER DISSIPATION (W) The AVDD33 supply powers the DAC core circuitry. The power dissipation of the AVDD33 supply rail is independent of the digital operating mode and sample rate. The current drawn from the AVDD33 supply rail is typically 98 mA (320 mW) when the full-scale current of the four main DACs (DAC 1, DAC 2, DAC 3, and DAC 4) is set to the nominal value of 20 mA.
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AD9148 Data Sheet 0.25 0.35 0.23 0.30 0.20 POWER (W) 0.18 0.20 0.15 0.15 0.13 0.10 0.08 0.10 0.05 0.05 0.03 0 Figure 88. CVDD18 Power Dissipation vs. fDAC, PLL Disabled 300 280 260 240 08910-087 fDATA (MSPS) 220 fDAC (MSPS) 200 1000 180 900 160 800 140 700 120 600 100 500 60 400 80 300 40 200 0 100 20 0 0 08910-086 POWER (W) 0.25 Figure 89. DVDD18 Power Dissipation vs. fDATA Due to Inverse Sinc Filter Rev.
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Data Sheet AD9148 TEMPERATURE SENSOR The AD9148 has a diode-based temperature sensor for measuring the temperature of the die. The temperature reading is accessed by Register 0x5E and Register 0x5F. The temperature of the die can be calculated as TDIE = TA = TDIE – PD × TJA = 50 – 0.8 × 18 = 35.6°C (DieTemp[15 : 0] − 13,700) 130 where: TA is the ambient temperature in degrees Celsius. TJA is the thermal resistance from junction to ambient of the AD9148 as shown in Table 7.
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AD9148 Data Sheet INTERRUPT REQUEST OPERATION The AD9148 provides an interrupt request output signal (Pin H4, IRQ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output. Pull the IRQ pin high external to the device.
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Data Sheet AD9148 INTERFACE TIMING VALIDATION The AD9148 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected and stored.
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AD9148 Data Sheet EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9148, certain sequences should be followed. An example start-up routine using the following device configuration is used for this example. START-UP SEQUENCE • • • • • • • • • • • The power clock and register write sequencing for reliable device start-up follows: fDATA = 122.88 MSPS Interpolation = 4×, using HB1 = ’00’ and HB2 = ’000’ Input data = baseband data Dual port mode with 1 DCI fOUT = 140 MHz fREFCLK = 122.
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Data Sheet AD9148 OUTLINE DIMENSIONS A1 BALL CORNER 12.10 12.00 SQ 11.90 A1 BALL CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P 10.40 BSC SQ 0.80 BSC TOP VIEW 0.80 REF BOTTOM VIEW DETAIL A *1.30 MAX DETAIL A 0.96 0.70 0.35 NOM 0.30 MIN 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER *COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1 WITH EXCEPTION TO PACKAGE HEIGHT. Figure 93. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] BC-196-7 Dimensions shown in millimeters Rev.
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AD9148 Data Sheet 8.20 REF SQ 11.20 REF SQ TOP VIEW 1.50 1.32 1.17 A1 BALL PAD CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 10.40 BSC SQ 0.80 BSC 0.80 REF DETAIL A 0.75 REF A B C D E F G H J K L M N P DETAIL A BOTTOM VIEW 1.09 0.99 0.89 0.38 0.33 0.28 0.24 REF SEATING PLANE 0.53 0.48 0.43 BALL DIAMETER COPLANARITY 0.12 COMPLIANT TO JEDEC STANDARDS MO-192. 02-07-2012-A A1 BALL PAD CORNER 12.10 12.00 SQ 11.90 Figure 94.
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Data Sheet AD9148 NOTES Rev.