Datasheet

Data Sheet AD9119/AD9129
Rev. A | Page 65 of 68
Table 59. Bit Descriptions for Parity Err Falling
Bits Bit Name Description Reset Access
[7:0] Parity falling edge error count Number of falling edge-based errors detected, clipped to 256 0x00 R
Delay Control Register 0
Address: 0x70, Reset: 0xFF, Name: Delay Ctrl 0
Table 60. Bit Descriptions for Delay Ctrl 0
Bits Bit Name Description Reset Access
[7:0]
Enable delay cell
Sets each bit to enable or disable the delay cell, Bits[7:0]; delay cell number corresponds to bit
number
1: enables delay cell (default)
0: disables delay cell
0xFF
R/W
Delay Control Register 1
Address: 0x71, Reset: 0x67, Name: Delay Ctrl 1
Table 61. Bit Descriptions for Delay Ctrl 1
Bits Bit Name Description Reset Access
[7:3] Reserved Reserved 0x60 R/W
[2:0] Enable delay cell
Sets each bit to enable or disable the delay cell, Bits[10:8]; delay cell numbers are 10, 9,
and 8, which correspond to Bit 2, Bit 1, and Bit 0, respectively
1: enables delay cell (default)
0: disables delay cell
0x7 R/W
Drive Strength Register
Address: 0x7C, Reset: 0x7C, Name: Drive Strength
Table 62. Bit Descriptions for Drive Strength
Bits Bit Name Description Reset Access
[7:6] DCO drive strength Sets DCO drive strength
00: 2 mA
01: 2.8 mA (default)
10: 3.4 mA
11: 4 mA
0x1 R/W
[5:0] Reserved Reserved 0x3C R/W
Part ID Register
Address: 0x7F, Reset: 0x03 or 0x83, Name: Part ID
Table 63. Bit Descriptions for Part ID
Bits Bit Name Description Reset Access
[7:0] Part ID Version information
0x07 = the AD9129 (14-bit version)
0x87 = the AD9119 (11-bit version)
0x07
or
0x87
R