Datasheet

AD9119/AD9129 Data Sheet
Rev. A | Page 64 of 68
Sample Error Detection (SED) Data Port 0 Falling Edge Status Low Register
Address: 0x55, Reset: 0x00, Name: SED Patt/Err F0L
Table 53. Bit Descriptions for SED Patt/Err F0L
Bits Bit Name Description Reset Access
[7:0] SED Data Port 0 falling edge low part error bits SED Data Port 0 falling edge error, Bits[7:0] 0x00 R/W
Sample Error Detection (SED) Data Port 0 Falling Edge Status High Register
Address: 0x56, Reset: 0x000, Name: SED Patt/Err F0H
Table 54. Bit Descriptions for SED Patt/Err F0H
Bits Bit Name Description Reset Access
[7:6] Reserved Reserved 0x0 R
[5:0] SED Data Port 0 falling edge high part error bits SED Data Port 0 falling edge error, Bits[13:8] 0x00 R/W
Sample Error Detection (SED) Data Port 1 Falling Edge Status Low Register
Address: 0x57, Reset: 0x00, Name: SED Patt/Err F1L
Table 55. Bit Descriptions for SED Patt/Err F1L
Bits Bit Name Description Reset Access
[7:0] SED Data Port 1 falling edge low part error bits SED Data Port 1 falling edge error, Bits[7:0] 0x00 R/W
Sample Error Detection (SED) Data Port 1 Falling Edge Status High Register
Address: 0x58, Reset: 0x00, Name: SED Patt/Err F1H
Table 56. Bit Descriptions for SED Patt/Err F1H
Bits Bit Name Description Reset Access
[7:6] Reserved Reserved 0x0 R
[5:0] SED Data Port 1 falling edge high part error bits SED Data Port 1 falling edge error, Bits[13:8] 0x00 R/W
Parity Control Register
Address: 0x5C, Reset: 0x00, Name: Parity Control
Table 57. Bit Descriptions for Parity Control
Bits
Bit Name
Description
Reset
Access
7 Parity enable 1: enables parity 0x00 R/W
6 Parity even
1: even parity. Even parity is defined as XOR[FRM(n), P0_D0(n),
P0_D1(n), P0_D2(n), ..., P0_D13(n), P1_D0(n), P1_D1(n),
P1_D2(n), …, P1_D13(n)] = 0.
0: odd parity. Odd parity is defined as XOR[FRM(n), P0_D0(n),
P0_D1(n), P0_D2(n), ..., P0_D13(n), P1_D0(n), P1_D1(n),
P1_D2(n), …, P1_D13(n)] = 1
Note that the parity bit must be enabled in Register 0x07.
0 R/W
5 Parity error clear 1: clears parity error counters 0 R/W
[4:2]
Reserved
Reserved
0x0
R
1 Parity error falling edge 1: signals detection of a falling edge parity error 0 R
0 Parity error rising edge 1: signals detection of a rising edge parity error 0 R
Parity Rising Edge Count Register
Address: 0x5D, Reset: 0x00, Name: Parity Err Rising
Table 58. Bit Descriptions for Parity Err Rising
Bits Bit Name Description Reset Access
[7:0] Parity rising edge error count Number of rising edge-based errors detected, clipped to 256 0x00 R
Parity Falling Edge Count Register
Address: 0x5E, Reset: 0x00, Name: Parity Err Falling