Datasheet
AD9119/AD9129 Data Sheet
Rev. A | Page 62 of 68
Analog Control 1 Register
Address: 0x22, Reset: 0x00, Name: ANA_CNT1
Table 42. Bit Descriptions for ANA_CNT1
Bits Bit Name Description Reset Access
[7:0] Reserved Reserved 0x0 R/W
Analog Control 2 Register
Address: 0x23, Reset: 0x0C, Name: ANA_CNT2
Table 43. Bit Descriptions for ANA_CNT2
Bits Bit Name Description Reset Access
[7:0] Reserved Reserved 0x0C R/W
Clock Control 1 Register
Address: 0x30, Reset: 0x00, Name: CLK REG1
Table 44. Bit Descriptions for CLK REG1
Bits Bit Name Description Reset Access
7 Reserved Must be set to 0; reserved 0 R/W
6 Cross enable Enables zero-crossing control 0 R/W
[5:2] Cross location Adjusts zero-crossing control location (signed magnitude) 0 R/W
1 Duty enable Enables duty cycle correction 0 R/W
0 Select internal Must be set to 0 0 R/W
Retimer Control 0 Register
Address: 0x33, Reset: 0x30, Name: Retimer Ctrl 0
Table 45. Bit Descriptions for Retime Ctrl 0
Bits Bit Name Description Reset Access
[7:4] Phase step 4-bit signed magnitude; PFD phase step = n × 30° 0x3 R/W
3 Clear lost Clear lost status bit 0
2 PLL divider 1: divide-by-4
0: divide-by-8
0
[1:0] Retimer mode 0: enable PFD, normal mode
1: reserved
2: reserved
3: reserved
0x0
Retimer Control 1 Register
Address: 0x34, Reset: 0x55, Name: Retimer Ctrl 1
Table 46. Bit Descriptions for Retimer Ctrl 1
Bits Bit Name Description Reset Access
[7:4]
Reserved
Reserved
0x5
R/W
3 PLL reset_Z 1: normal operation for DAC clock PLL
0: resets the DAC clock PLL
0 R/W
[2:0] Reserved Reserved 0x5 R/W
Retimer Status 0 Register
Address: 0x35, Reset: 0x00, Name: Retimer Stat 0
Table 47. Bit Descriptions for Retimer Stat 0
Bits Bit Name Description Reset Access
7 PLL lock 1: retimer PLL locked 0 R
6 PLL lost 1: retimer PLL lost (can be sticky) 0 R
[5:4] Reserved Reserved 0x0 R
[3:0] Reserved Reserved 0x0 R