Datasheet

Data Sheet AD9119/AD9129
Rev. A | Page 61 of 68
Data Mode Control Register
Address: 0x18, Reset: 0x00, Name: Data Mode Ctrl
Table 37. Bit Descriptions for Data Mode Ctrl
Bits Bit Name Description Reset Access
7 Filter enable 1: enables 2× interpolation filter
0: bypasses 2× interpolation filter
0 R/W
6 Binary select Selects input data format
1: unsigned
0: signed (Twos complement)
0 R/W
5 FILT_SEL 2× interpolator filter select
1: 40 dB OOB rejection
0: 25 dB out-of-band (OOB) rejection
0 R
[4:0] Reserved Reserved 0 R
Decoder Control (Program Thermometer Type) Register
Address: 0x19, Reset: 0x00, Name: Decode Ctrl
Table 38. Bit Descriptions for Decode Ctrl
Bits Bit Name Description Reset Access
[7:1] Reserved Reserved 0x00 R
0 Mix-Mode enable 1: Mix-Mode
0: normal
0 R/W
Sync Control Register
Address: 0x1A, Reset: 0x00, Name: Sync
Table 39. Bit Descriptions for Sync
Bits Bit Name Description Reset Access
7 Inc latency Increment delay by 1 0 R/W
6 Dec latency Decrement delay by 1 0 R/W
5 Reserved Reserved 0 R
4
Sync enable
1: multi-DAC sync output pin enabled
0: multi-DAC sync output pin disabled
0
R/W
3 Sync done 1: last increment or decrement request is complete 0 R
[2:0] Phase readback Readback of existing SYNC phase delay value 0 R
Full-Scale Current Adjust (Lower) Register
Address: 0x20, Reset: 0x00, Name: FSC_1
Table 40. Bit Descriptions for FSC_1
Bits Bit Name Description Reset Access
[7:0] Full-scale current, Bits[7:0] DAC gain adjust; DAC full-scale current (LSB) 0x00 R/W
Full-Scale Current Adjust (Upper) Register
Address: 0x21 Reset: 0x02, Name: FSC_2
Table 41. Bit Descriptions for FSC_2
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R/W
[6:2] Reserved Reserved 0 R
[1:0] Full-scale current, Bits[9:8] DAC gain adjust; DAC full-scale current (MSB) 0x02 R/W