Datasheet

AD9119/AD9129 Data Sheet
Rev. A | Page 60 of 68
FIFO Control Register
Address: 0x11, Reset: 0x00, Name: FIFO Ctrl
Table 31. Bit Descriptions for FIFO Ctrl
Bits Bit Name Description Reset Access
7 SPIFrmReq Requests a SPI-based FIFO alignment (FIFO reset) 0 R/W
6 SPIFrmAck Acknowledges SPIFrmReq change (tracks SPIFrmReq setting) 0 R/W
5 Enable pin framing 1: enables hardware pin-based FIFO framing 0 R/W
[4:1] Reserved Reserved 0x0 R
0 Phase report enable 1: enables FIFO phase reporting 0 R/W
FIFO Offset Register
Address: 0x12, Reset: 0x04, Name: FIFO Offset
Table 32. Bit Descriptions for FIFO Offset
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R
[6:4] RdPtrOff[2:0] FIFO read pointer offset 0x0 R/W
3 Reserved Reserved 0 R
[2:0] WtPtrOff[2:0] FIFO write pointer offset 0x4 R/W
FIFO Thermometer for Phase 0 Status Register
Address: 0x13, Reset: 0x00, Name: FIFO PH0 THRM
Table 33. Bit Descriptions for FIFO PH0 THRM
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R
[6:0] Phz0Thrm
Phase 0-based FIFO thermometer status. Phase 0 relative FIFO phasing, as 0000000b
to 1111111b, where 0000011b is considered the middle of the FIFO storage space.
0x00 R
FIFO Thermometer for Phase 1 Status Register
Address: 0x14, Reset: 0x00, Name: FIFO PH1 THRM
Table 34. Bit Descriptions for FIFO PH1 THRM
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R
[6:0] Phz1Thrm
Phase 1-based FIFO thermometer status. Phase 1 relative FIFO phasing, as 0000000b
to 1111111b, where 0000011b is considered the middle of the FIFO storage space.
0x00 R
FIFO Thermometer for Phase 2 Status Register
Address: 0x15, Reset: 0x00, Name: FIFO PH2 THRM
Table 35. Bit Descriptions for FIFO PH2 THRM
Bits Bit Name Description Reset Access
7
Reserved
Reserved
0
R
[6:0] Phz2Thrm
Phase 2-based FIFO thermometer status. Phase 2 relative FIFO phasing, as 0000000b
to 1111111b, where 0000011b is considered the middle of the FIFO storage space.
0x00 R
FIFO Thermometer for Phase 3 Status Register
Address: 0x16, Reset: 0x00, Name: FIFO PH3 THRM
Table 36. Bit Descriptions for FIFO PH3 THRM
Bits Bit Name Description Reset Access
7 Reserved Reserved 0 R
[6:0] Phz3Thrm
Phase 3-based FIFO thermometer status. Phase 3 relative FIFO phasing, as 0000000b
to 1111111b, where 0000011b is considered the middle of the FIFO storage space.
0x00 R