Datasheet

AD9119/AD9129 Data Sheet
Rev. A | Page 56 of 68
DEVICE CONFIGURATION REGISTER DESCRIPTIONS
SPI Communications Control Register
Address: 0x00, Reset: 0x81, Name: Mode
Table 18. Bit Descriptions for Mode
Bits Bit Name Description Reset Access
7 SDIO_DIR Selects 3-wire or 4-wire mode
1: 3-wire bidirectional
0: 4-wire unidirectional
1 R/W
6 LSB/MSB LSB/MSB data packing
1: LSB-first packing
0: MSB-first packing
0 R/W
5 SoftReset 1: performs a software-based reset 0 R/W
4 Reserved Must be set to 0; reserved (short addressing mode) 0 R/W
3 Reserved Mirror Bit 4 for safety 0 R
2 SoftReset Mirror Bit 5 for safety 0 R
1 LSB/MSB Mirror Bit 6 for safety 0 R
0
SDIO_DIR
Mirror Bit 7 for safety
1
R
Power Control Register
Address: 0x01, Reset: 0x48, Name: Power-Down
Table 19. Bit Descriptions for Power-Down
Bits Bit Name Description Reset Access
7 BG_PD Band gap power-down
1: band gap is powered down
0: band gap is active
0 R/W
6 IREF_PD I
REF
power-down
1: FSC is 0 mA
0: FSC is as programmed
1 R/W
5 BIAS_PD Bias power-down
1: all bias currents are off
0: all bias currents are on
0 R/W
4 Reserved Reserved 0 R/W
3 Reserved Must be set to 1; reserved 1 R/W
2 CLKPATH_PD Clock path power-down
1: DAC clock is powered down
0: DAC clock is active
0 R/W
1 Retimer_PD 1: PLL is powered down 0 R/W
0 DLL_PD DLL (data receiver) power-down
1: DLL (data receiver) is powered down
0 R/W