Datasheet

Data Sheet AD9119/AD9129
Rev. A | Page 55 of 68
DEVICE CONFIGURATION REGISTERS
DEVICE CONFIGURATION REGISTER MAP
The blank bits in Table 17 are reserved and should be programmed to their default values. A setting of 1 or 0 indicates the required
programming for the bit.
Table 17. Device Configuration Register Map
Register Name
Address
Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Hex Dec
Mode 0x00 0 R/W SDIO_DIR LSB/MSB SoftReset 0 0 SoftReset LSB/MSB SDIO_DIR 0x81
Power-Down 0x01 1 R/W BG_PD IREF_PD BIAS_PD 1 CLKPATH_PD Retimer_PD DLL_PD 0x48
IRQ Enable 0 0x03 3 R/W FIFO_Warn2 FIFO_Warn1 SPIFrmAck DLL warn DLL lock Retimer lost Retimer lock 0x00
IRQ Enable 1 0x04 4 R/W AED pass AED fail SED fail Parity err fall Parity err rise 0x00
IRQ Request 0 0x05 5 R/W FIFO_Warn2 FIFO_Warn1 SPIFrmAck DLL warn DLL lock Retimer lost Retimer lock 0x00
IRQ Request 1
0x06
6
R/W
AED pass
AED fail
SED fail
Parity err fall
Parity err rise
0x00
Frame Pin Usage 0x07 7 R/W ParUsage FrmUsage FRM_x pin usage mode, Bits[1:0] 0x00
Reserved_0 0x08 8 R/W Must maintain default (reset) value of 0x58 0x58
Data Ctrl 0 0x0A 10 R/W DLL enable Duty cycle
correction
enable
Phase offset, Bits[3:0] 0x40
Data Ctrl 1 0x0B 11 R/W Warn clear Lock delay
divider
Controller clock divider,
Bits[1:0]
Delay line middle set, Bits[3:0] 0x29
Data Ctrl 2 0x0C 12 R/W DCO enable Maximum delay set, Bits[2:0] Minimum delay set, Bits[2:0] 0x23
Data Ctrl 3 0x0D 13 R/W Duty correction BW, Bits[1:0] 0x04
Data Status 0 0x0E 14 R DLL lock DLL warn DLL delay line
start warning
DLL delay line
end warning
DLL correct
phase
DCI on DLL lock phase DLL running N/A
FIFO Ctrl
0x11
17
R/W
SPIFrmReq
SPIFrmAck
Enable pin
framing
Phase report
enable
0x00
FIFO Offset 0x12 18 R/W RdPtrOff, Bits[2:0] WtPtrOff, Bits[2:0] 0x04
FIFO Ph0 Thrm 0x13 19 R Phz0Thrm, Bits[6:0] N/A
FIFO Ph1 Thrm 0x14 20 R Phz1Thrm, Bits[6:0] N/A
FIFO Ph2 Thrm 0x15 21 R Phz2Thrm, Bits[6:0] N/A
FIFO Ph3 Thrm
0x16
22
R
Phz3Thrm, Bits[6:0]
N/A
Data Mode Ctrl 0x18 24 R/W Filter enable Binary select FILT_SEL 0x00
Decode Ctrl 0x19 25 R/W Mix-Mode en 0x00
Sync 0x1A 26 R/W Inc latency Dec latency Sync enable Sync done Phase readback, Bits[2:0] 0x00
FSC_1 0x20 32 R/W Full-scale current, Bits[7:0] 0x00
FSC_2 0x21 33 R/W Full-scale current, Bits[9:8] 0x02
ANA_CNT1 0x22 34 R/W 0x00
ANA_CNT2 0x23 35 R/W 0x0C
CLK REG1 0x30 48 R/W 0 Cross enable Cross location, Bits[3:0] Duty enable 0 0x00
Retimer Ctrl 0 0x33 51 R/W Phase step, Bits[3:0] Clear lost PLL divider Retimer mode, Bits[1:0] 0x30
Retimer Ctrl 1 0x34 52 R/W PLL reset_Z 0x55
Retimer Stat 0 0x35 53 R PLL lock PLL lost N/A
SED Control 0x50 80 R/W SED enable SED error clear AED enable 0 0 AED pass AED fail SED fail 0x00
SED Patt/Err R0L 0x51 81 R/W SED Data Port 0 rising edge low part error, Bits[7:0] N/A
SED Patt/Err R0H 0x52 82 R/W SED Data Port 0 rising edge high part error, Bits[13:8] N/A
SED Patt/Err R1L 0x53 83 R/W SED Data Port 1 rising edge low part error, Bits[7:0] N/A
SED Patt/Err R1H 0x54 84 R/W SED Data Port 1 rising edge high part error, Bits[13:8] N/A
SED Patt/Err F0L 0x55 85 R/W SED Data Port 0 falling edge low part error, Bits[7:0] N/A
SED Patt/Err F0H 0x56 86 R/W SED Data Port 0 falling edge high part error, Bits[13:8] N/A
SED Patt/Err F1L 0x57 87 R/W SED Data Port 1 falling edge low part error, Bits[7:0] N/A
SED Patt/Err F1H 0x58 88 R/W SED Data Port 1 falling edge high part error, Bits[13:8] N/A
Parity Control 0x5C 92 R/W Parity enable Parity even Parity error
clear
Parity error
falling edge
Parity error
rising edge
0x00
Parity Err Rising 0x5D 93 R Parity rising edge error count, Bits[7:0] N/A
Parity Err Falling 0x5E 94 R Parity falling edge error count, Bits[7:0] N/A
Delay Ctrl 0 0x70 112 R/W Enable delay cell, Bits[7:0] 0xFF
Delay Ctrl 1 0x71 113 R/W Enable delay cell, Bits[10:8] 0x67
Drive Strength 0x7C 124 R/W DCO drive strength, Bits[1:0] 0x7C
Part ID 0x7F 127 R Part ID, Bits[7:0] 0x07 or
0x87