Datasheet

AD9119/AD9129 Data Sheet
Rev. A | Page 52 of 68
Peak DAC Output Power Capability
The maximum peak power capability of a differential current
output DAC is dependent on its peak differential ac current,
I
PEAK
, and the equivalent load resistance it sees. In the case of a
1:1 balun with 50 source termination, the equivalent load that
is seen by the DAC ac current source is 25 . If the AD9119/
AD9129 is programmed for an I
OUTFS
= 20 mA, its peak ac current
is 9.375 mA and its peak power, delivered to the equivalent
load, is 2.2 mW (that is, P = I
2
R). Because the source and load
resistance seen by the 1:1 balun are equal, this power is shared
equally. Hence, the output load receives 1.1 mW, or 0.4 dBm
peak power.
To calculate the rms power delivered to the load, consider the
following:
Peak-to-rms of digital waveform
Any digital backoff from digital full scale
DAC sinc response and nonideal losses in the external
network
For example, a reconstructed sine wave with no digital backoff
ideally measures −2.6 dBm because it has a peak-to-rms ratio of
3 dB. If a typical balun loss of 0.4 dBm is included, the user would
expect to measure 3 dBm of actual power in the region where
the sinc response of the DAC has negligible influence. Increasing
the output power is best accomplished by increasing I
OUTFS
.
Output Stage Configuration
The AD9119/AD9129 are intended to serve high dynamic range
applications that require wide signal reconstruction bandwidth
(that is, a DOCSIS cable modem termination system (CMTS))
and/or high IF/RF signal generation. Optimum ac performance
can be realized only if the DAC output is configured for differential
(that is, balanced) operation with its output common-mode
voltage biased to a stable, low noise 1.8 V nominal analog supply
(VDDA). The ADP150 LDO can be used to generate a clean 1.8
V supply.
The output network used to interface to the DAC should provide
a near 0 dc bias path to VDDA. Any imbalance in the output
impedance over frequency between the IOUTP and IOUTN pins
degrades the distortion performance (mostly even order) and
noise performance. Component selection and layout are critical
in realizing the performance potential of the AD9119/AD9129.
Most applications that require balanced-to-unbalanced conversion
from 10 MHz to 1 GHz can take advantage of the Mini-Circuits
JTX series of transformers that offer impedance ratios of both
2:1 and 1:1.
Figure 152 shows the AD9119/AD9129 interfacing to the JTX-2-
10T transformer. This transformer provides excellent amplitude/
phase balance (that is, <1 dB/1°) up to 1 GHz while providing
a 0 Ω D dc bias path to VDDA. If filtering of the DAC images
and clock components is required, applying an analog LC filter
on the single-ended side has the advantage of preserving the
balance of the transformer.
JTX-2-10T+
MINI-CIRCUITS
50Ω
50Ω
IOUTP
IOUTN
VDDA
2:1
11149-156
Figure 152. Recommended Transformer for Wideband Applications with
Upper Bandwidths of up to 2.2 GHz
Figure 153 shows an interface that can be considered when
interfacing the DAC output to a self-biased differential gain block.
The inductors (L) shown serve as RF chokes that provide the
dc bias path to AGND. Its value, along with the dc blocking
capacitors, determines the lower cut-off frequency of the
composite pass-band response. (The dc blocking capacitors
form a high-pass response with the input resistance of the RF
differential gain stage.)
100Ω
IOUTP
IOUTN
L
L
RF DIFF_
AMP
C
C
VDDA
11149-157
Figure 153. Interfacing the DAC Output to Self-Biased,
Differential Gain Stage
Many RF differential amplifiers consist of two single-ended
amplifiers with matched gain, thus providing no common-mode
rejection while possibly degrading the balance, due to poor
matching characteristics. Also, depending on the component
tolerances, differential LC filters can further degrade the balance
in a differential signal path. In both cases, the use of a balun could
be advantageous in rejecting the common-mode distortion and
noise components from the RF DAC prior to filtering or further
amplification.