Datasheet

Data Sheet AD9119/AD9129
Rev. A | Page 5 of 68
SERIAL PORT AND CMOS PIN SPECIFICATIONS
VDDA = VDD = 1.8 V, VSSA = −1.5 V, I
OUTFS
= 33 mA, T
A
= −40°C to +85°C.
Table 4
.
Parameter Symbol Test Comments/Conditions Min Typ Max Unit
WRITE OPERATION See Figure 126
SCLK Clock Rate f
SCLK
, 1/t
SCLK
20 MHz
SCLK Clock High t
HIGH
20 ns
SCLK Clock Low t
LOW
20 ns
SDIO to SCLK Setup Time t
DS
10 ns
SCLK to SDIO Hold Time
t
DH
5
ns
CS to SCLK Setup Time
t
S
10 ns
SCLK to CS Hold Time
t
H
5 ns
READ OPERATION
See Figure 127
SCLK Clock Rate f
SCLK
, 1/t
SCLK
20 MHz
SCLK Clock High t
HIGH
20 ns
SCLK Clock Low t
LOW
20 ns
SDIO to SCLK Setup Time t
DS
10 ns
SCLK to SDIO Hold Time t
DH
5 ns
CS to SCLK Setup Time
t
S
10 ns
SCLK to SDIO (or SDO) Data Valid Time t
DV
10 ns
CS to SDIO (or SDO) Output Valid to High-Z
t
EZ
2
INPUTS (SDI, SDIO, SCLK, CS)
Voltage In High V
IH
1.2 1.8 V
Voltage In Low V
IL
0 0.4 V
Current In High I
IH
+75 µA
Current In Low I
IL
−150 µA
OUTPUTS (SDIO, SYNC)
Voltage Out High V
OH
1.3 2.0 V
Voltage Out Low V
OL
0 0.3 V
Current Out High
I
OH
4
mA
Current Out Low I
OL
4 mA