Datasheet
Data Sheet AD9119/AD9129
Rev. A | Page 47 of 68
INTERRUPT REQUESTS
The AD9119/AD9129 can provide the host processor with an
interrupt request output signal (IRQ), indicating that one or
more of the following events has occurred:
One of the clock controllers has established or lost lock.
A parity error has occurred.
A sample error detection status or result is ready.
The FIFO is nearing an overwrite status.
The IRQ output signal is an active low output signal that is available
on the IRQ pin (Pin H2). If used, connect the output to VDD via
a 10 kΩ pull-up resistor.
Each IRQ is enabled by setting the enable bits in Register 0x03
and Register 0x04 that have the same bit mapping as the IRQ
status bits in Registers 0x05 and Register 0x06. If an interrupt bit
is not enabled, a read request of that bit shows a direct readback
of the current state of the source. Thus, a read request of either
register shows the current state of all eight interrupts in that
register, regardless of whether each individual bit is actually
enabled to generate an interrupt. When an interrupt bit is enabled,
it captures a rising edge of the interrupt source and holds it,
even if the source subsequently returns to its zero state. It is
possible, for example, for the retimer lost interrupt enable and
retimer lock interrupt enable status bits (Register 0x03[1:0],
respectively) to be set when a controller temporarily loses lock
but then reestablishes lock before the IRQ is serviced by the host.
In such a case, the host should validate the present status of the
suspect block by reading back its current status bits. Based on
the status of these bits, the host can take appropriate action, if
required.
The IRQ pin responds only to those interrupts that are enabled. To
clear an IRQ, it is necessary to write a 1b to the bit in Register 0x05
or Register 0x06 that caused the interrupt. See Figure 141 for
a detailed diagram of the interrupt circuitry.
The IRQ can also be used during the AD9119/AD9129
initialization phase after power-up to determine when the
retimer PLL and data receiver controllers achieve lock. For
example, before enabling the retimer PLL, the retimer lock
interrupt enable bit (Register 0x03[0]) can be set, and the IRQ
output signal can be monitored to determine when lock is
established, before continuing in a similar manner with the data
receiver controller. Clear the relevant lock bit, after locking, before
continuing to the next controller. When all of the controllers are
locked, set the appropriate lost lock enable bits in Register 0x03
to continuously monitor the controllers for loss of lock.
R
QD
WRITE 1b TO
REQUEST BIT
IRQ ENABLE
SOURCE
IRQ REQUEST
IRQ ENABLE
IRQ ENABLE
IRQ PIN
OTHER IRQ
BITS
SINGLE IRQ BIT
11149-144
Figure 141. Interrupt Request Circuitry
Table 15. Interrupt Request Registers
Addr (Hex) Bit Bit Name Description
0x05 7 FIFO_Warn2 interrupt status Indicates that the FIFO is within two slots of overwrite
6 FIFO_Warn1 interrupt status Indicates that the FIFO is within one slot of overwrite
5 SPIFrmAck interrupt status Indicates acknowledgement that the SFrmReq bit has changed from 0b to 1b
4 Reserved Reserved
3 DLL warn interrupt status Indicates that the DLL is close to coming unlocked and action is needed
2 DLL lock interrupt status Indicates that the DLL is now locked
1 Retimer lost interrupt status Indicates that the retimer PLL is no longer locked
0 Retimer lock interrupt status Indicates that the retimer PLL is now locked
0x06 7 Reserved Reserved
6 AED pass interrupt status Indicates that the AED logic has captured eight valid samples
5 AED fail interrupt status Indicates that the AED logic has detected a miscompare
4 SED fail interrupt status Indicates that the SED logic has detected a miscompare
3 Parity error falling edge status Indicates a parity fault due to data captured on the falling edge
2 Parity error rising edge status Indicates a parity fault due to data captured on the rising edge
1 Reserved Reserved
0 Reserved Reserved