Datasheet

AD9119/AD9129 Data Sheet
Rev. A | Page 46 of 68
0 200 400 600 800 1000 1200
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
FREQUENCY (MHz)
MAGNITUDE (Normalized to 0dB)
11149-141
Figure 138. FIR25 2× Interpolation Filter Plot, Pass-Band Ripple; f
DAC
= 2.5 GHz
0 0.90.80.70.60.50.40.30.20.1 1.0
–60
–50
–55
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
NORMALIZED FREQUENCY (×π RAD/Sample)
MAGNITUDE (dB)
11149-142
Figure 139. FIR40 2× Interpolation Filter Plot, Complete Frequency Response
0 0.450.400.350.300.250.200.150.100.05 0.50
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
NORMALIZED FREQUENCY (×π RAD/Sample)
MAGNITUDE (dB)
11149-143
Figure 140. FIR40 2× Interpolation Filter Plot, Pass-Band Ripple
Pipeline Delay (Latency)
The pipeline delay, or latency, of the AD9129 varies, based on
the configuration that is chosen and can be calculated using the
following formula:
Pipeline_Total = Pipeline_Delay + 2×_Delay
+ Group_Delay + FIFO_Level
The values listed in Table 13 can be used, depending on the
mode of operation that is selected.
Table 13. Pipeline Delay Values for Each Block
Mode
Pipeline
Delay
(f
DAC
cycles)
Group
Delay
(f
DAC
cycles)
Total
Pipeline
(f
DAC
cycles)
Total
Delay
(f
DAC
cycles)
No 2× filter 74 N/A 74 74
With FIR25 43 2 117 119
With FIR40 67 9 141 150
The terms used in Table 13 are defined as follows:
• Pipeline delay is the time from DAC code latched until the
DAC output begins to move.
• Group delay is the time for the maximum amplitude pulse
to reach the DAC output, as compared to the first time the
output moves.
• No 2× filter is the base pipeline delay, including data
interface, analog circuitry (six cycles), and data FIFO at
half-full/Position 3.
• FIR25 is the 2× interpolator with 25 dB of out-of-band
rejection.
• FIR40 is the 2× interpolator with 40 dB of out-of-band
rejection.
Note that the values for pipeline delay apply in both normal
mode and Mix-Mode. After the total delay through the digital
blocks is calculated, add the FIFO level to that delay to find the
total pipeline delay. Note that the pipeline delay can be considered
fixed, with the only ambiguity being the FIFO state. The FIFO
state can be initialized as part of the startup sequence to ensure
a four sample spacing and, therefore, a fixed pipeline delay, or
deterministic latency (see the Resetting the FIFO Data Level
section for more information).
To ensure repeatable pipeline delay over multiple power-up cycles,
the SYNC output of the DAC must be aligned with a known system
sync reference. Follow a calibration process that is similar to the
multiple DAC sync process (see the Multiple DAC Synchronization
section for more information) after each power-up event to align
the DAC to the system sync reference.
Power-Up Time
The AD9119/AD9129 have a power-down register (Register 0x01)
that enables the user to power down various portions of the DAC.
The power-up time for several usage cases is shown in Table 14.
The recommended way to power up the AD9119/AD9129 is
to power up all parts of the circuit with I
REF
disabled (by setting
Register 0x01, Bit 6 = 1b), and then enable I
REF
by programming
Register 0x01, Bit 6 = 0b.
Table 14. Power-Up Times for Several Usage Cases
State Register State Time (µs)
Power-Up
From 0x01 = 0xEF to 0x01 = 0x08
250
Clock Path Up From 0x01 = 0x0C to 0x01 = 0x08 220
Wake-Up From 0x01 = 0x48 to 0x01 = 0x08 2