Datasheet

AD9119/AD9129 Data Sheet
Rev. A | Page 44 of 68
Figure 136 shows an example of two AD9119/AD9129 devices
that are synchronized to the same host (that is, FPGA or ASIC).
Note that, when the same resources are used to generate these out-
put signals, synchronization to a single host IC ensures minimum
data and DCI time skew between devices.
Synchronization within a data sample requires insight into the
difference between the read pointers of the master and slave
devices, as well as the ability to vary the delay of the slave device(s)
within the host to compensate for initial offsets between devices.
It is possible to calculate how many data samples the slave device(s)
is offset from the master device for the following reasons:
 The pipeline delay of each device is the same after FIFO
initialization (FIFO reset).
 The read counter of each device is derived from the same
phase aligned DACCLK source.
 The state of the read counters of each device is sampled at
the same instance in time via the FRAME signal.
 The readback value (Register 0x12[6:4]) is normalized to
a data sample (that is, a DACCLK period).
By calculating the difference between the read pointer settings
of the master and slave devices, the user can advance or delay
the data stream of the slave device within the FPGA. Because
this difference can be up to ±4 data samples, the FPGA must
provide this adjustment range for DAC synchronization alone.
Note that additional range must be added to compensate for any
other system delay variation.
In addition to synchronizing to the data sample level, the AD9119/
AD9129 can enable synchronization to the DACCLK level (see
Figure 135). A 1.8 V CMOS output pin, SYNC, can be used to
provide a DACCLK/8 signal. Using the SYNC output from each
DAC, enabled by Register 0x1A, Bit 4 = 1, the user can create
a simple phase detector with an external XOR gate.
DAC 1
SYNC
DAC 2
SYNC
XOR
11149-139
Figure 135. Example of Synchronization of Two DACs to
±1 DACCLK Accuracy
By adjusting the internal delay (incrementing or decrementing
by one DACCLK cycle with each write to Register 0x1A, Bit 7 or
Bit 6, respectively), the user can align the DACCLKs inside the two
DACs to within ±1 DACCLK cycle, when errors from the external
phase detector, low-pass filter, and delay differences are taken
into account. The existing phase position can be read from
Register 0x1A, Bits[2:0]. The value of each DAC in Register 0x1A
Bits[2:0] can be different when the DACs are synchronized. Align
the SYNC outputs first, then reset the FIFOs on each DAC to
ensure that proper sync is achieved.
This calibration must be performed at each power-up because
the FIFOs can be reset to any of four levels based on the divide-
by-4 output of the clock distribution block (see Figure 133). For
example, a FIFO reset to Level 2 could have an actual FIFO level
of 1.5, 1.75, 2, or 2.25, based on the location of the div-by-4 clock
edge. Adjusting the SYNC signals to align with each other
eliminates this ambiguity. As with the Sync register (0x1A
Bits[2:0]), the FIFO levels on each DAC do not have to match
(i.e., can be different) when the DACs are synchronized.
The FIFO set or reset level is always a whole number (the
recommended value is 2). Because of this, there is a possibility
that the FIFO can be reset on the border of a rollover from a
fractional level to a whole level (as in 1.75 to 2.0). In this case,
an effect can occur that causes the FIFO Read level to increment
before the final read, thereby shifting the level from 1.75 to 2.75
and thus effectively setting the level to 3 instead of 2. This can
be noticed by a seeming 4 DAC sample offset in the output.
To avoid this issue (setting the FIFO before emptying its last
read), the FIFO must be reset and then read back to understand
its level. If it is a whole number, it is recommended that the DCI
is advanced or delayed by 1 DACCLK cycle relative to the FIFO.
This must be done in the FPGA if DCO is used as the timing
reference for DCI. If this is not possible in the FPGA, then it is
recommended that the DCO NOT be used to generate DCI, in
order to decouple the two clocks and enable this necessary phase
shift. If the DCI is generated independently from the DCO,
then the 1 DACCLK delay or advance can be accomplished by
incrementing or decrementing by 1 the SYNC output of both
DACs in the same direction.
When the two DACs are aligned, the drift over temperature and
supply voltage of the SYNC signal of one DAC, relative to
another DAC, is expected to be no more than 450 ps.
The DCO signal is derived from the SYNC signal such that if
the SYNC signal is adjusted by a DACCLK cycle, the DCO
signal will also be adjusted by the same amount.
When all adjustments of the SYNC signal are complete, it is
recommended to disable the SYNC output by programming
Register 0x1A, Bit 4 = 0, to eliminate a possible source of clock
spurious signals.