Datasheet

Data Sheet AD9119/AD9129
Rev. A | Page 43 of 68
After the input data has been captured, the data is passed through a
logic block that monitors and/or determines the signal integrity
of the high speed digital data interface. The optional parity check
is used to continuously monitor the digital interface on a sample-
per-sample basis, and the sample error detection (SED) can be
used to validate the input data interface for system debug/test
purposes. Note that the FRAME and PARITY signals share the
same pin assignment because the FRAME signal is typically
used during system initialization (for FIFO synchronization
purposes), and parity is used in normal operation.
FIFO Description
The next functional block in the datapath is a set of four FIFOs
that are eight registers deep. The dual port data is clocked into
the FIFOs on both the rising and the falling edge of the DCI signal.
The FIFO acts as a buffer that absorbs timing variations between
the data source and DAC, such as the clock-to-data variation of
an FPGA or ASIC. For the greatest timing margin, maintain the
FIFO level near half full (that is, a difference of four between the
write and read pointers). The value of the write pointer determines
the FIFO register into which the input data is written, and the
value of the read pointer determines the register from which data
is read and fed into the data assembler. The write and read pointers
are updated every time new data is loaded and removed,
respectively, from the FIFO.
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow or become empty. Note that an overflow or
empty condition of the FIFO is the same as the write pointer and
read pointer being equal. When both pointers are equal, an
attempt is made to simultaneously read and write a single FIFO
register. This simultaneous register access leads to unreliable
data transfer through the FIFO and must be avoided by ensuring
that data is written to the FIFO at the same rate that data is read
from the FIFO, keeping the data level in the FIFO constant.
This condition must be met by ensuring that DCI is equal to
DACCLK/4 (or equivalently, DCO).
Resetting the FIFO Data Level
FIFO initialization is required to ensure a four-sample spacing
and a deterministic pipeline latency. If the clocks are running
at power-up, the FIFO initializes to 50% full. The AD9119/
AD9129 has an internal delay that effectively offsets the FIFO
pointers by 2, such that the optimal FIFO data level of 4 (center)
reads back as 2 (0000011b) from Register 0x13 to Register 0x16.
To achieve this level, set Register 0x12 to 0x20 (hexadecimal) before
resetting the FIFO. This sets the read pointer to Level 2 and the
write pointer to Level 0.
To maximize the timing margin between the DCI input and the
internal DAC data rate clock, initialize the FIFO data level before
beginning data transmission. The value of the FIFO data level
can be initialized in three ways: by resetting the device, by strobing
the FRM_x input, and via a write sequence to the serial port.
The two preferred methods are use of the FRAME signal and
via a write sequence to the serial port. Before initializing the
FIFO data level, the LVDS DLL and the DAC clock PLL must be
locked.
The FRM_x input can be used to initialize the FIFO data level
value. First, set up the FRM_N and FRM_P pins for frame mode
(Register 0x07, Bits[1:0] = 2). Next, assert the FRAME signal
high for at least one DCI clock cycle. When the FRAME signal is
asserted in this manner, the write pointer is set to 4 (by default
or to the FIFO start level (Register 0x12, Bits[2:0])) the next
time the read pointer becomes 0 (see Figure 134).
0 1 2 3
4 5
6
7 0 1 2 3
3 4
5 6 7 0 1 2 4 5 6 7
FIFO WRITE RESETS
READ
POINTER
FRAME
WRITE
POINTER
11149-137
Figure 134. Timing of the Frame Input vs. Write Pointer Value
To initialize the FIFO data level through the serial port, toggle
Bit 7 of Register 0x11 from 0b to 1b. When the write to the
register is complete, the FIFO data level is initialized.
The recommended procedure for a serial port FIFO data level
initialization is as follows:
1. Request FIFO level reset by setting Register 0x11, Bit 7,
to 1b.
2. Verif y that the part acknowledges the request by ensuring
that Register 0x11, Bit 6, is set to 1b.
3. Remove the request by setting Register 0x11, Bit 7, to 0b.
4. Verif y that the part drops the acknowledge signal by
ensuring that Register 0x11, Bit 6, is set to 0b.
Monitoring the FIFO Status
The relative FIFO data levels can be read from Register 0x13
through Register 0x16 at any time. The FIFO data level reported
by the serial port is denoted as a 7-bit thermometer code of the
write counter state, relative to the absolute read counter being at 0.
For example, the FIFO data level of 2 is reported as a value of
0000011b in the status register. Adding the internal delay of 2 to
this value makes the reported FIFO level equal to 4. It should be
noted that, depending on the timing relationship between DCI
and the main DACCLK signal, the FIFO level value can be off by
a count of ±1. Therefore, it is important that the difference
between the read and write pointers be maintained at ≥2.
Multiple DAC Synchronization
Synchronization of multiple AD9119/AD9129s implies that all
of the DAC outputs are time aligned to the same phase when all
devices are fed with the same data pattern (along with DCI) at
the same instance of time. FIFO initialization ensures that the
initial pipeline latency in the FIFO is set to four samples and
remains at this level, assuming that no process, voltage, or tem-
perature variations occur between the host and the AD9119/
AD9129 clock domains.