Datasheet

Data Sheet AD9119/AD9129
Rev. A | Page 37 of 68
MSB/LSB TRANSFERS
The AD9119/AD9129 serial port can support both MSB-first
and LSB-first data formats. This functionality is controlled by
the LSB/MSB bit, Bit 6 in Register 0x00. The default is MSB first
(LSB/MSB = 0). When the MSB-first data format is selected, the
instruction and data bytes must be written from the most
significant bit to the least significant bit.
When LSB/MSB = 1 (LSB first), the instruction and data bytes
must be written from the least significant bit to the most
significant bit.
SERIAL PORT CONFIGURATION
The AD9119/AD9129 serial port configuration is controlled
by Register 0x00, Bits[7:5]. Note that the configuration changes
immediately upon writing to the last bit of the register. When
setting the software reset bit (SoftReset in Register 0x00, Bit 5),
all registers are set to their default values except Register 0x00,
which remains unchanged.
In the event of unexpected programming sequences, the
AD9119/AD9129 SPI can become inaccessible. For example,
if user code inadvertently changes the LSB/MSB bit, the bits that
follow experience unexpected results. The SPI can be returned
to a known state by writing an incomplete byte (1 to 7 bits) of
all 0s, followed by three bytes of 0x00. This returns to the MSB-
first instructions (Register 0x00 = 0x00) so that the device can
be reinitialized.
R/W A6 A5 A4 A3 A2 A1 A0
D7
N
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
SDIO
CS
11149-127
Figure 122. Serial Register Interface Timing, MSB-First Write
R/W A6 A5 A4 A3 A2 A1 A0
D7
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
SDIO
SDO
D7
CS
11149-128
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
Figure 123. Serial Register Interface Timing, MSB-First Read
A0 A1 A2 A3 A4 A5 A6R/W
SCLK
SDIO
CS
INSTRUCTION CYCLE D
A
TA TRANSFER CYCLE
11149-129
D7
N
D6
N
D5
N
D0
0
D1
0
D2
0
D4
0
Figure 124. Serial Register Interface Timing, LSB-First Write
A0 A1 A2 A3 A4 A5 A6R/W
D0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SCLK
SDIO
SDO
D0
CS
11149-130
D7
N
D6
N
D5
N
D1
0
D2
0
D4
0
D7
N
D6
N
D5
N
D1
0
D2
0
D4
0
Figure 125. Serial Register Interface Timing, LSB-First Read
INSTRUCTION BIT 6INSTRUCTION BIT 7
SCLK
SDIO
t
DS
t
DS
t
DH
t
SCLK
CS
11149-131
Figure 126. Timing Diagram for an SPI Register Write
I1 I0 D7 D6 D5
t
DV
t
DNV
SCLK
SDIO
CS
11149-132
Figure 127. Timing Diagram for an SPI Register Read
After the last instruction bit is written to the SDIO pin, the
driving signal must be set to a high impedance in time for the
bus to turn around. The serial output data from the AD9119/
AD9129 is enabled by the falling edge of SCLK. This causes the
first output data bit to be shorter than the remaining data bits,
as shown in Figure 127. To assure proper reading of data, read
the SDIO pin or the SDO pin before changing SCLK from low
to high. Due to the more complex multibyte protocol, multiple
AD9119/ AD9129 devices cannot be daisy-chained on the SPI bus.
Control multiple DACs by using independent
CS
signals.