Datasheet

AD9119/AD9129 Data Sheet
Rev. A | Page 36 of 68
SERIAL COMMUNICATIONS PORT OVERVIEW
The AD9119/AD9129 are 11-bit/14-bit DACs that operate at an
update rate of up to 2.85 GSPS. Due to internal timing
requirements, the minimum allowable sample rate is 1400
MSPS. Input data is sampled through two 11-/14-bit LVDS
ports that are internally multiplexed. Each port has its own data
inputs, but both ports share a common data clock input (DCI).
The LVDS inputs meet the IEEE-1596 specification with the
exception of input hysteresis, which is not guaranteed over all
process corners. Each DCI input runs at one-quarter the input
data rate in a double data rate (DDR) format. Each edge of the
DCI is used to transfer data into the AD9119/AD9129.
The DACCLK_N and DACCLK_P inputs directly drive the
DAC core to minimize clock jitter. The DACCLK signal is
divided by 4 and then output as the DCO for each port. The
DCO signal can be used to clock the data source. The DAC
expects DDR LVDS data (P0_D[13:0]x, P1_D[13:0]x), with
each channel aligned with the single DDR DCI signal.
Control of the AD9119/AD9129 functions is via a SPI.
SERIAL PERIPHERAL INTERFACE (SPI)
The AD9119/AD9129 SPI is a flexible, synchronous serial
communications port, allowing easy interface to many
industry-standard microcontrollers and microprocessors. The
serial I/O is compatible with most synchronous transfer formats,
including the Motorola® SPI and the Intel® SSR protocols. The
interface allows read/write access to all registers that configure
the AD9119/AD9129. Most significant bit first (MSB-first) or
least significant bit first (LSB-first) transfer formats are supported.
The AD9119/AD9129 serial interface port can be configured as
a single I/O pin (SDIO) or two unidirectional pins for input/
output (SDIO and SDO).
SDO (PIN J2)
SDIO (PIN J1)
SCLK (PIN K1)
CS (PIN K2)
AD9119/
AD9129
SPI PORT
11149-126
Figure 121. AD9119/AD9129 SPI Port
GENERAL OPERATION OF THE SPI
There are two phases to a communication cycle with the AD9119/
AD9129. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9119/AD9129, coincident with
the first eight SCLK rising edges. The instruction byte provides
the AD9119/AD9129 serial port controller with information
about the data transfer cycle, which is Phase 2 of the communi-
cation cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write and the starting register
address for the first byte of the data transfer. The first eight SCLK
rising edges of each communication cycle are used to write the
instruction byte into the AD9119/AD9129.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9119/
AD9129 and the system controller. Phase 2 of the communication
cycle is a transfer of one byte only. Single-byte data transfers are
useful to reduce CPU overhead when register access requires
one byte only. Registers change immediately upon writing to the
last bit of each transfer byte.
CS
(chip select) can be raised after
each sequence of eight bits (except the last byte) to stall the bus.
The serial transfer resumes when
CS
is lowered. Stalling on
nonbyte boundaries resets the SPI.
INSTRUCTION MODE (8-BIT INSTRUCTION)
The instruction byte is shown in the following table.
MSB LSB
I7 I6 I5 I4 I3 I2 I1 I0
R/W A6 A5 A4 A3 A2 A1 A0
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Logic 0 indicates a write
operation, the data transfer cycle. A6 to A0 (Bit 6 through Bit 0
of the instruction byte) determine which register is accessed
during the data transfer portion of the communications cycle.
SERIAL PERIPHERAL INTERFACE PIN
DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9119/AD9129 and to run the internal state machines. The
maximum frequency of SCLK is 20 MHz. All data input to the
AD9119/AD9129 is registered on the rising edge of SCLK. All
data is driven out of the AD9119/AD9129 on the rising edge
of SCLK.
CS
—Chip Select
Active low input starts and gates a communication cycle. It allows
more than one device to be used on the same serial communi-
cations lines. The SDO and SDIO pins go to a high impedance
state when this input is high. Chip select should stay low during
the entire communication cycle.
SDIO—Serial Data I/O
Data is always written into the AD9119/AD9129 on this pin.
However, this pin can be used as a bidirectional data line. The
configuration of this pin is controlled by Register 0x00, Bit 7
(SDIO_DIR). The default is Logic 1, which configures the SDIO
pin as bidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. When the AD9119/AD9129
are operating in a single bidirectional I/O mode, this pin does
not output data and is set to a high impedance state.