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11-/14-Bit, 5.7 GSPS,

RF Digital-to-Analog Converter

Data Sheet

AD9119/AD9129

Rev. A Document Feedback

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FEATURES

DAC update rate: up to 5.7 GSPS

Direct RF synthesis at 2.85 GSPS data rate

DC to 1.425 GHz in baseband mode

DC to 1.0 GHz in 2× interpolation mode

1.425 GHz to 4.2 GHz in Mix-Mode

Bypassable 2× interpolation

Excellent dynamic performance

Supports DOCSIS 3.0 wideband ACLR/harmonic performance

8 QAM carriers: ACLR > 65 dBc

Industry-leading single/multicarrier IF or RF synthesis

4-carrier W-CDMA ACLR at 2457.6 MSPS

OUT

= 900 MHz, ACLR = 71 dBc (baseband mode)

OUT

= 2100 MHz, ACLR = 68 dBc (Mix-Mode)

OUT

= 2700 MHz, ACLR = 67 dBc (Mix-Mode)

Dual-port LVDS and DHSTL data interface

Up to 1.425 GSPS operation

Source synchronous DDR clocking with parity bit

Low power: 1.0 W at 2.85 GSPS (1.3 W at 5.7 GSPS)

APPLICATIONS

Broadband communications systems

CMTS/VOD

Wireless infrastructure: W-CDMA, LTE, point-to-point

Instrumentation, automatic test equipment (ATE)

Radar, jammers

FUNCTIONAL BLOCK DIAGRAM

SDO

SDIO

SCLK

DCI_x

DATA ASSEMBLER

SPI

RESET

Tx DAC

CORE

DATA

LATCH

IOUTP

IOUTN

IRQ

4× FIFO

2×

BASEBAND

MODE

MIX-

MODE

FRM_x

(FRAME/

PARITY)

AD9129

CLOCK

DISTRIBUTION

VREFI250U

LVDS DDR

RECEIVER

LVDS DDR

RECEIVER

P1_D[13:0]P,

P1_D[13:0]N

P0_D[13:0]P,

P0_D[13:0]N

DLL

1.2V

PLL

DCO_x

NORMAL

11149-001

DACCLK_x

DCR

Figure 1.

GENERAL DESCRIPTION

The AD9119/AD9129 are high performance, 11-/14-bit RF digital-

to-analog converters (DACs) supporting data rates up to 2.85

GSPS. The DAC core is based on a quad-switch architecture that

enables dual-edge clocking operation, effectively increasing the

DAC update rate to 5.7 GSPS when configured for Mix-Mode™

or 2× interpolation. The high dynamic range and bandwidth

enable multicarrier generation up to 4.2 GHz.

In baseband mode, wide bandwidth capability combines with high

dynamic range to support from 1 to 158 contiguous carriers for

CATV infrastructure applications. A choice of two optional 2×

interpolation filters is available to simplify the postreconstruction

filter by effectively increasing the DAC update rate by a factor of 2.

In Mix-Mode operation, the AD9119/AD9129 can reconstruct

RF carriers in the second and third Nyquist zone while still

maintaining exceptional dynamic range up to 4.2 GHz. The

high performance NMOS DAC core features a quad-switch

architecture that enables industry-leading direct RF synthesis

performance with minimal loss in output power. The output

current can be programmed over a range of 9.5 mA to 34.4 mA.

The AD9119/AD9129 include several features that may further

simplify system integration. A dual-port, source synchronous

LVDS interface simplifies the data interface to a host FPGA/ASIC.

A differential frame/parity bit is also included to monitor the

integrity of the interface. On-chip delay locked loops (DLLs)

are used to optimize timing between different clock domains.

A serial peripheral interface (SPI) is used to configure the

AD9119/AD9129 and monitor the status of readback registers.

The AD9119/AD9129 is manufactured on a 0.18 µm CMOS

process and operates from +1.8 V and −1.5 V supplies. It is

supplied in a 160-ball chip scale package ball grid array.

PRODUCT HIGHLIGHTS

1. High dynamic range and signal reconstruction bandwidth

support RF signal synthesis of up to 4.2 GHz.

2. Dual-port interface with double data rate (DDR) LVDS

data receivers supports 2850 MSPS maximum conversion rate.

3. Manufactured on a CMOS process; a proprietary switching

technique enhances dynamic performance.

Summary of content (68 pages)

PAGE 1
1-/14-Bit, 5.7 GSPS, RF Digital-to-Analog Converter AD9119/AD9129 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM RESET I250U VREF IRQ AD9129 1.2V SPI DCO_x Tx DAC CORE IOUTP IOUTN 2× PLL CLOCK DISTRIBUTION DCR DACCLK_x 11149-001 DCI_x BASEBAND MODE DATA LATCH DLL DATA ASSEMBLER P0_D[13:0]P, P0_D[13:0]N P1_D[13:0]P, P1_D[13:0]N MIXNORMAL MODE LVDS DDR RECEIVER FRM_x (FRAME/ PARITY) 4× FIFO SDIO SDO CS SCLK LVDS DDR RECEIVER DAC update rate: up to 5.7 GSPS Direct RF synthesis at 2.
PAGE 2
AD9119/AD9129 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Peripheral Interface Pin Descriptions .......................... 36 Applications ....................................................................................... 1 MSB/LSB Transfers .................................................................... 37 Functional Block Diagram ..............................................................
PAGE 3
Data Sheet AD9119/AD9129 SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. Table 1.
PAGE 4
AD9119/AD9129 Data Sheet LVDS DIGITAL SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. LVDS drivers and receivers are compatible with the IEEE Standard 1596.3-1996, unless otherwise noted. Table 2.
PAGE 5
Data Sheet AD9119/AD9129 SERIAL PORT AND CMOS PIN SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. Table 4.
PAGE 6
AD9119/AD9129 Data Sheet AC SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C, unless otherwise noted. Table 5. Parameter DYNAMIC PERFORMANCE DAC Update Rate (DACCLK_x Inputs) Normal Mode, FIR25 Enabled, or FIR40 Enabled with VDD = 1.9 V FIR40 Filter Enabled, VDD = 1.8 V Adjusted DAC Update Rate 1 Output Settling Time to 0.
PAGE 7
Data Sheet AD9119/AD9129 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter DCI, DCO to VSS LVDS Data Inputs to VSS IOUTP, IOUTN to VSSA I250U, VREF to VSSA IRQ, CS, SCLK, SDO, SDIO, RESET, SYNC to VSS Junction Temperature Operating Temperature Range Storage Temperature Range Rating −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V VSSA − 0.3V to +2.5V VSSA − 0.3 V to VDDA + 0.3 V −0.3 V to VDD + 0.
PAGE 8
AD9119/AD9129 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A I250U VREF VSSA VSSA VDDA SH IOUTP IOUTN VDDA SH VDDA VDDA VDDA VSSC VSSC VSSC B VDDA VDDA VSSA VSSA VSSA VDDA SH VDDA SH VDDA VDDA VDDA VDDA VSSC VSSC SYNC C DACCLK_N VDDA VDDA VSSA VSSA VSSA VDDA VDDA VDDA VDDA VSSC VSSC VSS VSS D DACCLK_P VDDA VDDA VDDA VSSC VSSC VDDA VSSC VSSC VSSC VSSC VSS VSS VSS E VDDA VDDA VSSC VSSC
PAGE 9
Data Sheet AD9119/AD9129 Pin No. G12, G13, G14, H11, H12, H13, H14, J3, J4, J11, J12, J13, J14 C13, C14, D12, D13, D14, E11, E12, E13, E14, F11, F12, F13, F14, G1, G2, G3, G11, H3, H4 A12, A13, A14, B12, B13, C11, C12, D5, D6, D8, D9, D10, D11, E3, E4, F1, F2, F3, F4, G4 A6 A7 B14 C1, D1 H1 H2 Mnemonic VDD Description +1.8 V Digital Supply Voltage Input. VSS +1.8 V Digital Supply Return. VSSC Analog Supply Return.
PAGE 10
AD9119/AD9129 1 Data Sheet 2 3 4 5 6 7 8 9 10 11 12 13 14 A I250U VREF VSSA VSSA VDDA SH IOUTP IOUTN VDDA SH VDDA VDDA VDDA VSSC VSSC VSSC B VDDA VDDA VSSA VSSA VSSA VDDA SH VDDA SH VDDA VDDA VDDA VDDA VSSC VSSC SYNC C DACCLK_N VDDA VDDA VSSA VSSA VSSA VDDA VDDA VDDA VDDA VSSC VSSC VSS VSS D DACCLK_P VDDA VDDA VDDA VSSC VSSC VDDA VSSC VSSC VSSC VSSC VSS VSS VSS E VDDA VDDA VSSC VSSC VSS VSS VSS VSS F VSSC VSSC VSSC VSSC
PAGE 11
Data Sheet AD9119/AD9129 Pin No. A12, A13, A14, B12, B13, C11, C12, D5, D6, D8, D9, D10, D11, E3, E4, F1, F2, F3, F4, G4 A6 A7 B14 C1, D1 H1 H2 Mnemonic VSSC Description Analog Supply Return.
PAGE 12
AD9119/AD9129 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD9119 Static Linearity IOUTFS = 28 mA, nominal supplies, TA = 25°C, unless otherwise noted. 0.3 0.10 0.08 0.2 0.06 0.1 DNL (LSB) INL (LSB) 0.04 0 0.02 0 –0.02 –0.04 –0.06 –0.1 200 400 600 800 1000 1200 1400 1600 1800 2000 CODE –0.10 11149-004 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 CODE Figure 4. Typical INL, 11 mA at 25°C 11149-007 –0.08 –0.2 Figure 7. Typical DNL, 11 mA at 25°C 0.10 0.3 0.08 0.06 0.
PAGE 13
Data Sheet AD9119/AD9129 AC (Normal Mode) IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. REF 5dBm ATTEN: 24dB REF 5dBm ATTEN: 20dB 5 –5 –5 –15 –15 –25 –25 –35 –35 10dB/DIV –45 –55 –45 –55 –65 –65 –75 –75 –85 START 20MHz RES BW 20kHz VBW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) 11149-011 –85 –95 –95 START 20MHz RES BW 20kHz Figure 10. Single-Tone Spectrum at fOUT = 70 MHz VBW 20kHz STOP 2.6GHz SWEEP 7.
PAGE 14
AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –30 –45 –16dBFS –12dBFS –6dBFS 0dBFS –50 11mA 22mA 33mA –40 –55 SFDR (dBc) SFDR (dBc) –50 –60 –65 –60 –70 –70 –80 –75 400 600 800 1000 1200 1400 fOUT (MHz) 0 600 800 1000 1200 1400 1400 Figure 18. SFDR vs. fOUT over DAC IOUTFS –55 –16dBFS –12dBFS –6dBFS 0dBFS –50 400 fOUT (MHz) Figure 16. SFDR vs.
PAGE 15
Data Sheet AD9119/AD9129 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –150 –145 –40°C +25°C +85°C –40°C +25°C +85°C –150 NSD (dBm/Hz) NSD (dBm/Hz) –155 –155 –160 –160 –165 –165 400 600 800 1000 1200 1400 fOUT (MHz) 0 –40 –40 –50 –50 –60 –60 10dB/DIV –30 –70 –80 1000 1200 –80 –90 –100 –100 –110 –110 –120 SPAN 53.84MHz SWEEP 1.485s TOTAL CARRIER POWER –10.705dBm/3.84MHz LOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 5MHz 3.
PAGE 16
AD9119/AD9129 Data Sheet AC (Mix-Mode) IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. REF 0dBm ATTEN: 20dB 5 –10 –5 –20 –15 –30 –25 10dB/DIV –40 –50 REF 5dBm ATTEN: 20dB –35 –45 –60 –55 –70 –65 –80 –75 –85 START 20MHz RES BW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) VBW 20kHz 11149-029 –90 –100 –95 START 20MHz RES BW 20kHz Figure 24. Single Tone Spectrum at fOUT = 2350 MHz –40 STOP 2.6GHz SWEEP 7.
PAGE 17
Data Sheet AD9119/AD9129 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
PAGE 18
AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –145 –145 –40°C +25°C +85°C –40°C +25°C +85°C –150 NSD (dBm/Hz) NSD (dBm/Hz) –150 –155 –160 –155 –160 –165 1500 2000 2500 3500 3500 4000 fOUT (MHz) 1500 11149-043 –170 1000 3000 3500 3500 Figure 36. W-CDMA NSD vs. fOUT over Temperature –20 –30 –30 –40 –40 –50 –50 –60 –60 10dB/DIV –20 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 VBW 3kHz SPAN 53.
PAGE 19
Data Sheet AD9119/AD9129 DOCSIS Performance (Normal Mode) IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. REF –20dBm –20 REF –20dBm 1 –30 –30 –40 –40 –50 –50 –60 –60 10dB/DIV 10dB/DIV 1 –70 –80 –90 –70 –80 –90 –100 –110 –110 –120 –120 TRC 1 1 1 SCL f f f X 70MHz (Δ) 70MHz (Δ) 140MHz VBW 2kHz Y –3.819dBm (Δ) –74.107dB (Δ) –74.148dB STOP 1.1GHz SWEEP 27.
PAGE 20
AD9119/AD9129 Data Sheet IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –40 IN-BAND THIRD HARMONIC (dBc) –60 –70 –80 –90 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) Figure 44. Second Harmonic vs. fOUT Performance for One DOCSIS Carrier –80 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) Figure 47. Third Harmonic vs. fOUT Performance for One DOCSIS Carrier –40 IN-BAND THIRD HARMONIC (dBc) –50 –60 –70 –80 –90 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) Figure 45.
PAGE 21
Data Sheet AD9119/AD9129 –50 –50 –55 –55 –60 –60 –65 –65 ACPR (dBc) –70 –75 ACP1 ACP2 ACP3 ACP4 ACP5 –70 –75 –80 –80 ACP1 ACP2 ACP3 ACP4 ACP5 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) –90 0 0.2 –65 –65 ACPR (dBc) ACPR (dBc) –55 –60 –70 –75 –70 –75 –80 –80 –85 –85 –90 0.1 0.4 0.6 0.8 1.0 fOUT (GHz) 11149-168 –90 0.2 –20 0.3 0.4 0.5 0.6 0.7 0.8 0.9 REF –20dBm –30 –40 –60 –50 10dB/DIV –65 –70 –75 –60 –70 –80 –90 –80 –100 –85 –110 –90 0 0.2 0.4 0.6 0.
PAGE 22
AD9119/AD9129 Data Sheet AD9129 Static Linearity IOUTFS = 28 mA, nominal supplies, TA = 25°C, unless otherwise noted. 1.0 2.0 1.5 0.5 DNL (LSB) INL (LSB) 1.0 0.5 0 0 –0.5 –0.5 –1.0 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE –1.5 11149-065 –1.5 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE Figure 56. Typical INL, 11 mA at 25°C 11149-068 –1.0 Figure 59. Typical DNL, 11 mA at 25°C 2.0 1.0 1.5 0.5 DNL (LSB) INL (LSB) 1.0 0.5 0 0 –0.5 –0.5 –1.
PAGE 23
Data Sheet AD9119/AD9129 AC (Normal Mode) IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. ATTEN: 24dB 5 –5 –15 –15 –25 –25 –35 –35 10dB/DIV –5 –45 –55 –55 –65 –75 –75 –85 –85 START 20MHz RES BW 20kHz VBW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) –95 START 20MHz RES BW 20kHz Figure 62. Single-Tone Spectrum at fOUT = 70 MHz VBW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) Figure 65.
PAGE 24
AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –40 –45 –16dBFS –12dBFS –6dBFS 0dBFS –50 –16dBFS –12dBFS –6dBFS 0dBFS –50 –55 IMD (dBc) SFDR (dBc) –60 –60 –65 –70 –80 –70 –90 –100 0 200 400 600 800 1000 1200 1400 fOUT (MHz) 11149-077 0 800 1000 1200 –16dBFS –12dBFS –6dBFS 0dBFS –50 1400 Figure 71. IMD vs.
PAGE 25
Data Sheet AD9119/AD9129 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –50 –150 –40°C +25°C +85°C –55 –40°C +25°C +85°C –155 NSD (dBm/Hz) SFDR (dBc) –60 –65 –160 –70 –165 0 200 400 600 800 1000 1200 1400 fOUT (MHz) –170 11149-083 0 200 400 600 800 1000 Figure 74. SFDR vs. fOUT over Temperature Figure 77. W-CDMA NSD vs.
PAGE 26
AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –60 FIRST ACLR (dBc) SECOND ACLR (dBc) –65 –70 –70 –75 –80 –80 –85 –85 –90 700 750 800 850 900 950 1000 fOUT (MHz) –90 700 Figure 80. Single-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR) –60 –70 –70 ACLR (dBc) –65 –80 –85 –85 800 850 fOUT (MHz) 900 950 1000 Figure 81. Single-Carrier W-CDMA ACLR vs.
PAGE 27
Data Sheet AD9119/AD9129 AC (Mix-Mode) IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. REF 0dBm ATTEN: 20dB –5 –20 –15 –30 –25 –40 –35 –50 –60 –45 –55 –70 –65 –80 –75 –90 –85 –100 VBW 20kHz STOP 2.6GHz SWEEP 7.78s (1001 pts) ATTEN: 20dB –95 START 20MHz RES BW 20kHz Figure 84. Single-Tone Spectrum at fOUT = 2350 MHz STOP 2.6GHz SWEEP 7.
PAGE 28
AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
PAGE 29
Data Sheet AD9119/AD9129 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –145 –145 –40°C +25°C +85°C –40°C +25°C +85°C –150 NSD (dBm/Hz) NSD (dBm/Hz) –150 –155 –155 –160 –160 2000 2500 3000 3500 4000 fOUT (MHz) –165 1500 –30 –40 –40 –50 –50 –60 –60 10dB/DIV –30 –70 –80 –80 –90 –100 –100 –110 –110 –120 SPAN 53.84MHz SWEEP 1.485s TOTAL CARRIER POWER –9.445dBm/3.84MHz LOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 5MHz 3.84MHz –73.
PAGE 30
AD9119/AD9129 Data Sheet IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –50 FIRST ACLR (dBc) SECOND ACLR (dBc) –55 –60 –60 –65 –65 –70 –75 –75 –80 –85 –85 1.8 2.0 2.2 2.4 2.6 Figure 98. Single-Carrier W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR) –50 –55 –90 1.4 2.2 2.4 2.6 –50 –55 –65 –65 ACLR (dBc) –60 –70 –75 –75 –80 –85 –85 fOUT (GHz) 2.2 2.4 2.6 –90 1.4 11149-110 2.0 Figure 99. Single-Carrier W-CDMA ACLR vs.
PAGE 31
Data Sheet AD9119/AD9129 DOCSIS Performance (Normal Mode) IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. REF –20dBm –20 1 –30 –40 –40 –50 –50 –60 –60 –70 –80 –70 –80 –90 –90 2Δ1 2Δ1 3Δ1 3Δ1 –100 –100 –110 –110 –120 TRC 1 1 1 SCL f f (Δ) f (Δ) X 70MHz (Δ) 70MHz (Δ) 140MHz VBW 20kHz Y –3.611dBm (Δ) –72.929dB (Δ) –74.629dB START 0Hz RES BW 20kHz STOP 1.1GHz SWEEP 27.
PAGE 32
AD9119/AD9129 Data Sheet IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –40 IN-BAND THIRD HARMONIC (dBc) –50 –60 –70 –80 –70 –80 0.4 0.6 0.8 1.0 fOUT (GHz) 0 Figure 108. Second Harmonic vs. fOUT Performance for One DOCSIS Carrier 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) 11149-122 0.2 11149-119 0 Figure 111. Third Harmonic vs.
PAGE 33
Data Sheet AD9119/AD9129 IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –55 –60 –65 –65 ACPR (dBc) –60 –70 –75 –70 –75 –80 –80 –85 –85 ACP1 ACP2 ACP3 ACP4 ACP5 –90 –90 0.2 0.4 0.6 0.8 1.0 fOUT (GHz) 0 11149-219 0 0.2 –65 –65 ACPR (dBc) ACPR (dBc) –55 –60 –70 –75 –75 –80 –85 –85 0.4 0.6 0.8 1.0 fOUT (GHz) 11149-220 –90 Figure 115. Four-Carrier ACPR vs. fOUT –55 –60 –65 –70 –75 –80 –90 0 0.2 0.4 0.6 0.8 fOUT (GHz) 1.
PAGE 34
AD9119/AD9129 Data Sheet IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –20 –40 REF –20dBm ACLR IN GAP CHANNEL (dBc) –30 –40 –60 –70 –80 –90 –100 –60 –70 –80 –110 CENTER 77MHz RES BW 10kHz VBW 1kHz SPAN 60MHz SWEEP 6.08s (1001 pts) –90 0 0.2 0.4 0.6 0.8 fOUT (GHz) Figure 119. Gap Channel ACLR at 77 MHz Figure 120. Gap Channel ACLR vs. fOUT Rev. A | Page 34 of 68 1.
PAGE 35
Data Sheet AD9119/AD9129 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Spurious-Free Dynamic Range The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.
PAGE 36
AD9119/AD9129 Data Sheet SERIAL COMMUNICATIONS PORT OVERVIEW The AD9119/AD9129 are 11-bit/14-bit DACs that operate at an update rate of up to 2.85 GSPS. Due to internal timing requirements, the minimum allowable sample rate is 1400 MSPS. Input data is sampled through two 11-/14-bit LVDS ports that are internally multiplexed. Each port has its own data inputs, but both ports share a common data clock input (DCI).
PAGE 37
Data Sheet AD9119/AD9129 MSB/LSB TRANSFERS INSTRUCTION CYCLE When LSB/MSB = 1 (LSB first), the instruction and data bytes must be written from the least significant bit to the most significant bit. SDIO R/W A0 A1 A2 A3 D40 D5N D6N D7N A5 A6 D00 D10 D20 A4 Figure 124. Serial Register Interface Timing, LSB-First Write INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SERIAL PORT CONFIGURATION SCLK In the event of unexpected programming sequences, the AD9119/AD9129 SPI can become inaccessible.
PAGE 38
AD9119/AD9129 Data Sheet THEORY OF OPERATION The AD9119/AD9129 are 11-bit/14-bit DACs that are capable of reconstructing signal bandwidths up to 1.425 GHz while operating with an input data rate up to 2.85 GSPS. Figure 128 shows a top level functional diagram of the AD9119/AD9129. A high perfor-mance NMOS DAC delivers a signal dependent, differential current to a balanced external load referenced a nominal 1.8 V analog supply. The current source array of the DAC is referenced to an external −1.
PAGE 39
Data Sheet AD9119/AD9129 The data timing requirements are defined by a minimum data valid margin that is dependent on the data clock input skew, input data jitter, and the variations of the DLL delay line across delay settings. This margin is defined by subtracting from the data period any data skew, data jitter, and the keep-out window (KOW) that is defined by the sum of the set and hold times, as follows: LVDS DATA PORT INTERFACE The AD9119/AD9129 can operate with input data rates of up to 2.85 GSPS.
PAGE 40
AD9119/AD9129 Data Sheet Figure 131 shows the DSC set and hold times with respect to the DCI signal and data signals. DATA DCI Table 10 lists the values that are guaranteed over the operating conditions. These values were taken with 50% duty cycle and DCI swing of 450 mV p-p. For best performance, the duty cycle variation should be kept below ±5%, and the DCI input should be as high as possible, up to 800 mV p-p. Table 10.
PAGE 41
Data Sheet AD9119/AD9129 Before losing lock, the DLL controller issues a DLL warning by setting Register 0x0E, Bit 6, to 1b and setting either Bit 5 or Bit 4 to 1b. This setting indicates that the DLL is near to losing lock. If the DLL is going to reach the beginning of the delay line soon, the controller issues a start warning by setting Register 0x0E, Bit 5 and Bit 6 to 1b. This setting indicates that the DLL is at the start of the delay line, and losing lock is imminent.
PAGE 42
AD9119/AD9129 Data Sheet pin and more than one IRQ is enabled, check Register 0x06, Bits[3:2] when an IRQ event occurs to determine whether the IRQ was caused by a parity error. The IRQ can also be cleared by writing 1b to Register 0x06, Bit 2 or Register 0x06, Bit 3. For the AD9119, the data port is 11-bit instead of 14-bit, so P0_D11, P0_D12, P0_D13, P1_D11, P1_D12, and P1_D13 are not used in the calculation of the parity bit.
PAGE 43
Data Sheet AD9119/AD9129 FIFO Description The next functional block in the datapath is a set of four FIFOs that are eight registers deep. The dual port data is clocked into the FIFOs on both the rising and the falling edge of the DCI signal. The FIFO acts as a buffer that absorbs timing variations between the data source and DAC, such as the clock-to-data variation of an FPGA or ASIC.
PAGE 44
AD9119/AD9129 Data Sheet Figure 136 shows an example of two AD9119/AD9129 devices that are synchronized to the same host (that is, FPGA or ASIC). Note that, when the same resources are used to generate these output signals, synchronization to a single host IC ensures minimum data and DCI time skew between devices.
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Data Sheet AD9119/AD9129 MATCHED DELAYS COMMON CLOCK SOURCE 1.4GHz TO 2.8GHz 0+ dBm ADCLK925 DCI DCO_x DACCLK AD9129 MASTER DCI_x FRM_x 0+ dBm FPGA DCI_x DACCLK FRM_x AD9129 11149-138 SLAVE DCO_x Figure 136. Example of Synchronization of Two DACs to One FPGA 2× Digital Filter The AD9119/AD9129 include a bypassable 2× half-band interpolation filter to help simplify the analog reconstruction filter.
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AD9119/AD9129 Data Sheet The values listed in Table 13 can be used, depending on the mode of operation that is selected. 1.0 MAGNITUDE (Normalized to 0dB) 0.5 Table 13. Pipeline Delay Values for Each Block 0 Mode No 2× filter With FIR25 With FIR40 –0.5 –1.0 200 400 600 800 1000 1200 11149-141 • 0 FREQUENCY (MHz) • Figure 138. FIR25 2× Interpolation Filter Plot, Pass-Band Ripple; fDAC = 2.5 GHz • 5 0 –5 • MAGNITUDE (dB) –10 –15 • –20 –25 –30 –35 –40 –45 –50 0 0.1 0.2 0.3 0.
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Data Sheet AD9119/AD9129 retimer lock interrupt enable status bits (Register 0x03[1:0], respectively) to be set when a controller temporarily loses lock but then reestablishes lock before the IRQ is serviced by the host. In such a case, the host should validate the present status of the suspect block by reading back its current status bits. Based on the status of these bits, the host can take appropriate action, if required.
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AD9119/AD9129 Data Sheet INTERFACE TIMING VALIDATION The AD9119/AD9129 provide on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected and stored.
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Data Sheet AD9119/AD9129 ANALOG INTERFACE CONSIDERATIONS The AD9119/AD9129 use the quad-switch architecture shown in Figure 143. Only one pair of switches is enabled during a half-clock cycle, thus requiring each pair to be clocked on alternative clock edges. A key benefit of the quad-switch architecture is that it masks the code-dependent glitches that occur in the conventional twoswitch DAC architecture. When Mix-Mode is used, the output is effectively chopped at the DAC sample rate.
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AD9119/AD9129 Data Sheet CLOCK INPUT The AD9119/AD9129 contain a low jitter, differential clock receiver that is capable of interfacing directly to a differential or single-ended clock source. Because the input is self-biased to a nominal midsupply voltage of 1.25 V with a nominal impedance of 10 kΩ//2 pF, it is recommended that the clock source be ac-coupled to the DACCLK_x input pins with an external differential load of 100 Ω.
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Data Sheet AD9119/AD9129 VOLTAGE REFERENCE IOUTFS = 9.5mA – 34mA The AD9119/AD9129 output current is set by a combination of digital control bits and the I250U reference current, as shown in Figure 149. (9/17) × IOUTFS IPEAK = (8/17) × IOUTFS AC AD9129 FSC[9:0] – + 4kΩ VSSA CURRENT SCALING Figure 150. Equivalent DAC Output Circuit IFULLSCALE I250 Figure 149. Voltage Reference Circuit The reference current is obtained by forcing the band gap voltage across an external 4.
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AD9119/AD9129 Data Sheet The maximum peak power capability of a differential current output DAC is dependent on its peak differential ac current, IPEAK, and the equivalent load resistance it sees. In the case of a 1:1 balun with 50 Ω source termination, the equivalent load that is seen by the DAC ac current source is 25 Ω. If the AD9119/ AD9129 is programmed for an IOUTFS = 20 mA, its peak ac current is 9.375 mA and its peak power, delivered to the equivalent load, is 2.2 mW (that is, P = I2R).
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Data Sheet AD9119/AD9129 For applications that operate the AD9119/AD9129 in Mix-Mode with output frequencies extending beyond 2.2 GHz, the user may want to consider the circuit shown in Figure 154. This circuit uses a wideband balun (for example, −3 dB at 4.0 GHz), with a configuration that is similar to the example shown in Figure 152, to provide a dc bias path for the DAC outputs.
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AD9119/AD9129 Data Sheet START-UP SEQUENCE A small number of steps is required to program the AD9119/AD9129 to the proper operating state after the device is powered up. This sequence is listed in Table 16, along with an explanation of the purpose of each step. Table 16.
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Data Sheet AD9119/AD9129 DEVICE CONFIGURATION REGISTERS DEVICE CONFIGURATION REGISTER MAP The blank bits in Table 17 are reserved and should be programmed to their default values. A setting of 1 or 0 indicates the required programming for the bit. Table 17.
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AD9119/AD9129 Data Sheet DEVICE CONFIGURATION REGISTER DESCRIPTIONS SPI Communications Control Register Address: 0x00, Reset: 0x81, Name: Mode Table 18.
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Data Sheet AD9119/AD9129 Interrupt Enable Register 0 Address: 0x03, Reset: 0x00, Name: IRQ Enable 0 Table 20.
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AD9119/AD9129 Data Sheet Interrupt Status Register1 Address: 0x06, Reset: 0x00, Name: IRQ Request 1 Table 23.
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Data Sheet AD9119/AD9129 Data Receiver Control 1 Register Address: 0x0B, Reset: 0x29, Name: Data Ctrl 1 Table 27.
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AD9119/AD9129 Data Sheet FIFO Control Register Address: 0x11, Reset: 0x00, Name: FIFO Ctrl Table 31.
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Data Sheet AD9119/AD9129 Data Mode Control Register Address: 0x18, Reset: 0x00, Name: Data Mode Ctrl Table 37.
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AD9119/AD9129 Data Sheet Analog Control 1 Register Address: 0x22, Reset: 0x00, Name: ANA_CNT1 Table 42. Bit Descriptions for ANA_CNT1 Bits [7:0] Bit Name Reserved Description Reserved Reset 0x0 Access R/W Reset 0x0C Access R/W Reset 0 0 0 0 0 Access R/W R/W R/W R/W R/W Reset 0x3 0 0 Access R/W Analog Control 2 Register Address: 0x23, Reset: 0x0C, Name: ANA_CNT2 Table 43.
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Data Sheet AD9119/AD9129 Sample Error Detection (SED) Control Register Address: 0x50, Reset: 0x00, Name: SED Control Table 48.
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AD9119/AD9129 Data Sheet Sample Error Detection (SED) Data Port 0 Falling Edge Status Low Register Address: 0x55, Reset: 0x00, Name: SED Patt/Err F0L Table 53.
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Data Sheet AD9119/AD9129 Table 59.
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AD9119/AD9129 Data Sheet OUTLINE DIMENSIONS 12.10 12.00 SQ 11.90 14 13 12 11 10 9 8 7 6 5 4 3 2 A B C D E F G H J K L M N P 10.40 BSC SQ 0.80 BSC BOTTOM VIEW TOP VIEW DETAIL A DETAIL A 0.43 MAX 0.25 MIN 1.40 MAX A1 BALL CORNER 1 SEATING PLANE 1.00 MAX 0.85 MIN 0.55 0.50 0.45 BALL DIAMETER COPLANARITY 0.12 COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1. 11-18-2011-A A1 BALL CORNER Figure 157.
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Data Sheet AD9119/AD9129 NOTES Rev.