Datasheet

AD9125
Rev. 0 | Page 54 of 56
EXAMPLE START-UP ROUTINE
There are certain sequences that should be followed to ensure
reliable startup of the AD9125.
The example start-up routine assumes the following device
configuration:
•
f
DATA
= 122.88 MSPS
•
Interpolation = 4×, using HB1 = 10 and HB2 = 010010
•
Input data = baseband data
•
f
OUT
= 140 MHz
•
f
REFCLK
= 122.88 MHz
•
PLL = enabled
•
Fine NCO = enabled
•
Inverse SINC filter = enabled
•
Synchronization = enabled
The following PLL settings can be derived from the device
configuration:
•
f
DACCLK
= f
DATA
× Interpolation = 491.52 MHz
•
f
VCO
= 4 × f
DACCLK
= 1966.08 MHz (1 GHz < f
VCO
< 2.1 GHz)
•
N1 = f
DACCLK
/f
REFCLK
= 4
•
N2 = f
VCO
/f
DACCLK
= 4
The following NCO settings can be derived from the device
configuration:
•
f
NCO
= 2 × f
DATA
•
f
CARRIER
= f
OUT
− f
MODHB1
= 140 − 122.88 = 17.12 MHz
•
FTW = 17.12/(2 × 122.88) × 2
32
= 0x11D55555
Start-Up Sequence
The following procedure sets the power clock and register write
sequencing for reliable device start-up:
1.
Power up the device (no specific power supply sequence is
required).
2.
Apply stable REFCLK input signal.
3.
Apply stable DCI input signal.
4.
Issue a hardware reset (optional).
As a result, the device configuration register write sequence is
0x00 Æ 0x20 /* Issue software reset */
0x00 Æ 0x00
0x0C Æ 0xD1 /* Start PLL */
0x0D Æ 0xD9
0x0A Æ 0xC0
0x0A Æ 0x80
/* ??Verify PLL is locked?? */
Read 0x0E, expect Bit 7 = 1, Bit 6 = 0
Read 0x06, expect 0x5C
0x10 Æ 0x48 /* Choose data rate mode */
0x17 Æ 0x04 /* Issue software FIFO reset */
0x18 Æ 0x02
0x18 Æ 0x00
/* ??Verify FIFO reset?? */
Read 0x18, expect 0x05
Read 0x19, expect 0x07
0x1B Æ 0x84 /* Configure interpolation
filters */
0x1C Æ 0x04
0x1D Æ 0x24
0x1E Æ 0x01 /* Configure NCO */
0x30 Æ 0x55
0x31 Æ 0x55
0x32 Æ 0xD5
0x33 Æ 0x11
0x36 Æ 0x01 /* Update frequency tuning
word */
0x36 Æ 0x00