Datasheet

AD9125
Rev. 0 | Page 52 of 56
INTERRUPT REQUEST OPERATION
The AD9125 provides an interrupt request output signal (on
Pin 7,
IRQ
) that can be used to notify an external host processor
of significant device events. Upon assertion of the interrupt,
the device should be queried to determine the precise event that
occurred. The
IRQ
pin is an open-drain, active low output. Pull
the
IRQ
pin high external to the device. This pin can be tied to
the interrupt pins of other devices with open-drain outputs to
wire-OR these pins together.
Sixteen event flags provide visibility into the device. These 16
flags are located in the two event flag registers (Register 0x06
and Register 0x07). The behavior of each of the event flags
is independently selected in the interrupt enable registers
(Register 0x04 and Register 0x05). When the flag interrupt
enable is active, the event flag latches and triggers an external
interrupt. When the flag interrupt is disabled, the event flag
simply monitors the source signal and the external
IRQ
remains
inactive.
Figure 86 shows the
IRQ
-related circuitry. This diagram shows how
event flag signals propagate to the
IRQ
output. The INTERRUPT_
ENABLE signal represents one bit from the interrupt enable
registers. The EVENT_FLAG_SOURCE signal represents one
bit from the event flag registers. The EVENT_FLAG_SOURCE
signal represents one of the device signals that can be monitored,
such as the PLL_LOCKED signal from the PLL phase detector
or the FIFO_WARNING_1 signal from the FIFO controller.
When an interrupt enable bit is set high, the corresponding event
flag bit reflects a positively tripped signal (that is, latched on the
rising edge of the EVENT_FLAG_SOURCE signal). This signal
also asserts the external
IRQ
. When an interrupt enable bit is set
low, the event flag bit reflects the current status of the EVENT_
FLAG_SOURCE signal, but the event flag has no effect on the
external
IRQ
.
The latched version of an event flag (the INTERRUPT_SOURCE
signal) can be cleared in two ways. The recommended way is by
writing 1 to the corresponding event flag bit; however, a hardware
or software reset can also clear the INTERRUPT_SOURCE.
INTERRUPT SERVICE ROUTINE
The interrupt request management starts by selecting the set of
event flags that require host intervention or monitoring. Those
events that require host action should be enabled so that the
host is notified when they occur. For events requiring host
intervention, upon
IRQ
activation, run the following routine to
clear an interrupt request:
1.
Read the status of the event flag bits that are being monitored.
2.
Set the interrupt enable bit low so that the unlatched EVENT_
FLAG_SOURCE signal can be monitored directly.
3.
Perform any actions that are required to clear the EVENT_
SOURCE_FLAG signal. In many cases, no specific actions
are required.
4.
Read the event flag to verify that the EVENT_FLAG_
SOURCE signal has been cleared.
5.
Clear the interrupt by writing 1 to the event flag bit.
6.
Set the interrupt enable bits of the events to be monitored.
Note that some of the EVENT_FLAG_SOURCE signals are latched
signals. These are cleared by writing to the corresponding event
flag bit. Details of each of the event flags can be found in Table 11.
INTERRUPT_ENABLE
EVENT_FLAG_SOURCE
DEVICE_RESET
EVENT_FLAG
INTERRUPT
SOURCE
1
0
OTHER
INTERRUPT
SOURCES
IRQ
WRITE_1_TO_EVENT_FLAG
09016-054
Figure 86. Simplified Schematic of
IRQ
Circuitry