Datasheet

AD9125
Rev. 0 | Page 51 of 56
ADDITIONAL SYNCHRONIZATION FEATURES
The synchronization logic incorporates additional features that
provide means for querying the status of the synchronization,
improving the robustness of the synchronization, and enabling
a one-shot synchronization mode. These features are detailed in
the Sync Status Bits and Timing Optimization sections.
Sync Status Bits
When the sync locked bit (Register 0x12, Bit 6) is set, it indicates
that the synchronization logic has reached alignment. This
alignment is determined when the clock generation state machine
phase is constant. It takes between (11 + averaging) × 64 and
(11 + averaging) × 128 DACCLK cycles. This bit can optionally
trigger an
IRQ
, as described in the
section.
Interrupt Request Operation
When the sync lost bit (Register 0x12, Bit 7) is set, it indicates
a previously synchronized device has lost alignment. This bit is
latched and remains set until cleared by overwriting the register.
This bit can optionally trigger an
IRQ
, as described in the
section. Interrupt Request Operation
The sync phase readback bits (Register 0x13, Bits[7:0]) report
the current clock phase in a 6.2 format. Bits[7:2] report which
of the 64 states (0 to 63) the clock is currently in. When averaging
is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, ¾).
The lower two bits give an indication of the timing margin issues
that may exist. If the sync sampling is error free, the fractional
clock state should be 00.
Timing Optimization
The REFCLK signal is sampled by a version of the DACCLK. If
sampling errors are being detected, the opposite sampling edge
can be selected to improve the sampling point. The sampling
edge can be selected by setting Register 0x10, Bit 3 (1 = rising
and 0 = falling).
The synchronization logic resynchronizes when a phase change
between the REFCLK signal and the state of the clock generation
state machine exceeds a threshold. To mitigate the effects of
jitter and prevent erroneous resynchronizations, the relative
phase can be averaged. The amount of averaging is set by the
sync averaging bits (Register 0x10, Bits[2:0]) and can be set
from 1 to 128. The higher the number of averages, the more
slowly the device recognizes and resynchronizes to a legitimate
phase correction. Generally, the averaging should be made as large
as possible while still meeting the allotted resynchronization
time interval.
The value of the sync phase request bits (Register 0x11,
Bits[5:0]) is the state to which the clock generation state
machine resets upon initialization. By varying this value, the
timing of the internal clocks with respect to the REFCLK signal
can be adjusted. Every increment in the value of the sync phase
request bits (Register 0x11, Bits[5:0]) advances the internal
clocks by one DACCLK period. This offset can be used for two
purposes: to skew the outputs of two synchronized DAC
outputs in increments of the DACCLK period and to change the
relative timing between the DCI input and REFCLK. This may
allow for more optimal placement of the DCI sampling point in
data rate synchronization mode.
Table 27. Synchronization Setup and Hold Times
Parameter Min Max Unit
t
SKEW
−t
DACCLK
/2 +t
DACCLK
/2 ps
t
SV_SYNC
100 ps
T
H_SYNC
330 ps