Datasheet

AD9125
Rev. 0 | Page 48 of 56
REFCLKP(1)/
REFCLKN(1)
REFCLKP(2)/
REFCLKN(2)
DCI(2)
FRAME(2)
t
SKEW
t
SU_DCI
t
H_DCI
09016-050
Figure 82. Timing Diagram Required for Synchronizing Devices
DACCLKP/
DACCLKN
FRAME
REFCLKP/
REFCLKN
DCI
IOUT1P/
IOUT1N
DCI
DACCLKP/
DACCLKN
REFCLKP/
REFCLKN
FRAME
IOUT2P/
IOUT2N
SAMPLE
RATE CLOCK
LOW SKEW
CLOCK DRIVER
SYNC
CLOCK
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
FPGA
09016-051
Figure 83. Typical Circuit Diagram for Synchronizing Devices to a System Clock