Datasheet

AD9125
Rev. 0 | Page 47 of 56
MULTICHIP SYNCHRONIZATION
System demands may require that the outputs of multiple DACs
be synchronized with each other or with a system clock. Systems
that support transmit diversity or beam forming, where multiple
antennas are used to transmit a correlated signal, require multiple
DAC outputs to be phase aligned with each other. Systems with
a time division multiplexing transmit chain may require one or
more DACs to be synchronized with a system-level reference clock.
Multiple devices are considered synchronized to each other when
the state of the clock generation state machine is identical for all
parts and when time aligned data is being read from the FIFOs
of all parts simultaneously. Devices are considered synchronized
to a system clock when there is a constant, known relationship
among the clock generation state machine, the data being read
from the FIFO, and a particular clock edge of the system clock.
The AD9125 has provisions for enabling multiple devices to be
synchronized to each other or to a system clock.
The AD9125 supports synchronization in two modes: data rate
mode and FIFO rate mode. Each of these modes has a different
lowest rate clock that the synchronization logic attempts to syn-
chronize to. In data rate mode, the input data rate represents the
lowest synchronized clock. In FIFO rate mode, the FIFO rate,
which is the data rate divided by the FIFO depth of 8, represents
the lowest rate clock. The advantage of FIFO rate synchronization
is increased time between keep-out windows for DCI changes
relative to the DACCLK or REFCLK input.
When in data rate mode, the elasticity of the FIFO is not used to
absorb timing variations between the data source and the DAC,
resulting in keep-out widows repeating at the input data rate.
The method chosen for providing the DAC sampling clock directly
impacts the synchronization methods available. When the device
clock multiplier is used, only data rate mode is available. When
the DAC sampling clock is sourced directly, both data rate mode
and FIFO rate mode synchronization are available. This section
details the synchronization methods for enabling both clocking
modes and for querying the status of the synchronization logic.
SYNCHRONIZATION WITH CLOCK MULTIPLICATION
When using the clock multiplier to generate the DAC sample
rate clock, the REFCLK input signal acts both as the reference
clock for the PLL-based clock multiplier and as the synchronization
signal. To synchronize devices, distribute the REFCLK signal
with low skew to all of the devices that need to be synchronized.
Skew between the REFCLK signals of the devices shows up
directly as a timing mismatch at the DAC outputs.
The frequency of the REFCLK signal is typically equal to the
input data rate. The FRAME and DCI signals, along with the
data, can be created in the FPGA. A circuit diagram of a typical
configuration is shown in Figure 81.
SYSTEM
CLOCK
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
REFCLKP/
REFCLKN
FRAME
DCI
REFCLKP/
REFCLKN
FRAME
DCI
IOUT1P/
IOUT1N
IOUT2P/
IOUT2N
FPGA
09016-049
Figure 81. Typical Circuit Diagram for Synchronizing Devices
The Procedure for Synchronization when Using the PLL section
outlines the steps required to synchronize multiple devices. The
procedure assumes that the REFCLK signal is applied to all devices
and that the PLL of each device is phase locked to this signal. This
procedure must be carried out on each individual device.
Procedure for Synchronization when Using the PLL
To synchronize all devices,
1.
Configure the device for data rate mode and periodic
synchronization by writing 0xC0 to the Sync Control 1
register (Register 0x10). Additional synchronization
options are available.
2.
Read the Sync Status 1 register (Register 0x12) and verify that
the sync locked bit (Bit 6) is set high, indicating that the
device achieved back-end synchronization and that the
sync lost bit (Bit 7) is low. These levels indicate that the clocks
are running with a constant, known phase relative to the
sync signal.
3.
Reset the FIFO by strobing the FRAME signal high for the
time required to write two complete input data-words.
Resetting the FIFO ensures that the correct data is being
read from the FIFO.
To maintain synchronization, the skew between the REFCLK
signals of the devices must be less than t
SKEW
. There are also setup
and hold times to be observed among the DCI, the data of each
device, and the REFCLK signal. When resetting the FIFO, the
FRAME signal must be held high for the time interval required
to write two complete input data-words. A timing diagram of
the input signals is shown in Figure 82.
This example shows a REFCLK frequency equal to the data rate.
Although this is the most common situation, it is not strictly
required for proper synchronization. Any REFCLK frequency
that satisfies the following equation is acceptable:
f
SYNC_I
= f
DACCLK
/2
N
and f
SYNC_I
≤ f
DATA
where N = 0, 1, 2, or 3.
As an example, a configuration with 4× interpolation and clock
frequencies of f
VCO
= 1600 MHz, f
DACCLK
= 800 MHz, f
DATA
=
200 MHz, and f
SYNC_I
= 100 MHz is a viable solution.