Datasheet

AD9125
Rev. 0 | Page 3 of 56
FUNCTIONAL BLOCK DIAGRAM
MULTICHIP
SYNCHRONIZATION
D[31:0]
DATA
RECEIVER
FIFO HB1 HB2 HB3
NCO
AND
MOD
f
DATA
/2
PRE
MOD
HB1_CLK MODE HB2_CLK HB3_CLK INTP FACTOR PHASE CORRECTION
INTERNAL CLOCK TIMING AND CONTROL LOGIC
16
16
10
16
16
I OFFSET
Q OFFSET
INV
SINC
AUX
1.2G
DAC 1
16-BIT
IOUT1P
IOUT1N
AUX
1.2G
DAC 1
16-BIT
IOUT2P
IOUT2N
REF
AND
BIAS
FSADJ
DACCLKP
DACCLKN
REFCLKP
REFCLKN
REFIO
10
GAIN 1
10
GAIN 2
DACCLK
SERIAL
INPUT/OUTPUT
PORT
PROGRAMMING
REGISTERS
POWER-ON
RESET
SDO
SDIO
SCLK
CS
RESET
IRQ
0
1
CLOCK
MULTIPLIER
(2× TO 16×)
CLK
RCVR
CLK
RCVR
PLL CONTROL
SYNC
DAC CLK_SEL
DACCLK
PLL_LOCK
DCI
FRAME
INVSINC_CLK
09016-002
Figure 2. AD9125 Functional Block Diagram