Datasheet
AD9125
Rev. 0 | Page 28 of 56
Register
Name
Address
(Hex) Bits Name Description Default
SED Control 0x67 7 SED compare enable
1 = enables the SED circuitry. None of the flags in this
register or the values in Register 0x70 through
Register 0x73 are significant if the SED is not enabled.
0
5 Sample error detected
1 = indicates an error is detected. The bit remains set
until cleared. Any write to this register clears this bit to 0.
0
3 Autoclear enable
1 = enables autoclear mode. This activates Bit 1 and Bit
0 of this register and causes Register 0x70 through
Register 0x73 to be autocleared whenever eight
consecutive error-free sample data sets are received.
0
1 Compare fail
1 = indicates an error has been detected. This bit
remains high until it is autocleared by the reception of
eight consecutive error-free comparisons or until it is
cleared by writing to this register.
0
0 Compare pass 1 = indicates that the last sample comparison was error free. 0
Compare I0 LSBs 0x68 [7:0] Compare Value I0[7:0]
Compare Value I0[15:0] is the word that is compared
with the I0 input sample captured at the input interface.
B6
Compare I0 MSBs 0x69 [7:0] Compare Value I0[15:8] See Register 0x68. 7A
Compare Q0 LSBs 0x6A [7:0] Compare Value Q0[7:0]
Compare Value Q0[15:0] is the word that is compared
with the Q0 input sample captured at the input interface.
45
Compare Q0 MSBs 0x6B [7:0]
Compare Value
Q0[15:8]
See Register 0x6A EA
Compare I1 LSBs 0x6C [7:0] Compare Value I1[7:0]
Compare Value I1[15:0] is the word that is compared
with the I1 input sample captured at the input interface.
16
Compare I1 MSBs 0x6D [7:0] Compare Value I1[15:8] See Register 0x6C. 1A
Compare Q1 LSBs 0x6E [7:0] Compare Value Q1[7:0]
Compare Value Q1[15:0] is the word that is compared
with the Q1 input sample captured at the input interface.
C6
Compare Q1 MSBs 0x6F [7:0]
Compare Value
Q1[15:8]
See Register 0x6E. AA
SED I LSBs 0x70 [7:0]
Errors Detected
I_BITS[7:0]
Errors detected I_BITS[15:0] indicates which bits were
received in error.
0
SED I MSBs 0x71 [7:0]
Errors detected
I_BITS[15:8]
See Register 0x70. 0
SED Q LSBs 0x72 [7:0]
Errors detected
Q_BITS[7:0]
Errors detected Q_BITS[15:0] indicates which bits were
received in error.
0
SED Q MSBs 0x73 [7:0]
Errors detected
Q_BITS[15:8]
See Register 0x72. 0
Die Revision 0x7F [5:2] Revision[3:0] Corresponds to device die revision. 3
1
All bit event flags are cleared by writing the respective bit high.