Datasheet

AD9125
Rev. 0 | Page 26 of 56
Register
Name
Address
(Hex) Bits Name Description Default
FTW 1 (LSB) 0x30 [7:0] FTW[7:0]
FTW[31:0] is the 32-bit frequency tuning word that
determines the frequency of the complex carrier
generated by the on-chip NCO. The frequency is not
updated when the FTW registers are written. The values
are only updated when Bit 0 of Register 0x36 transitions
from 0 to 1.
0
FTW 2 0x31 [7:0] FTW[15:8] See Register 0x30. 0
FTW 3 0x32 [7:0] FTW[23:16] See Register 0x30. 0
FTW 4 (MSB) 0x33 [7:0] FTW[31:24] See Register 0x30. 0
NCO Phase Offset
LSB
0x34 [7:0] NCO phase offset[7:0]
NCO phase offset[15:0] sets the phase of the complex
carrier signal when the NCO is reset. The phase offset
spans between 0° and 360°. Each bit represents an offset of
0.0055°. The value is in twos complement format.
0
NCO Phase Offset
MSB
0x35 [7:0] NCO phase offset[15:8] See Register 0x34. 0
NCO FTW Update 0x36 5
FRAME FTW
acknowledge
1 = indicates that the NCO has been reset due to an
extended FRAME pulse signal.
0
4 FRAME FTW request
0 → 1 = the NCO is reset on the first extended FRAME
pulse after this bit transitions from 0 to 1.
0
1
Update FTW
acknowledge
1 = indicates that the FTW has been updated. 0
0 Update FTW request
0 → 1 = the FTW is updated on 0-to-1 transition of this bit.
0
I Phase Adj LSB 0x38 [7:0] I phase adjust[7:0]
I phase adjust[9:0] is used to insert a phase offset
between the I and Q datapaths. This can be used to
correct for phase imbalance in a quadrature modulator.
See the Quadrature Phase Correction section for details.
0
I Phase Adj MSB 0x39 [1:0] I phase adjust[9:8] Register 0x38. 0
Q Phase Adj LSB 0x3A [7:0] Q phase adjust[7:0]
Q phase adjust[9:0] is used to insert a phase offset
between the I and Q datapaths. This can be used to
correct for phase imbalance in a quadrature modulator.
See the Quadrature Phase Correction section for details.
0
Q Phase Adj MSB 0x3B [1:0] Q phase adjust[9:8] See Register 0x3A. 0
I DAC Offset LSB 0x3C [7:0] I DAC offset[7:0]
I DAC offset[15:0] is a value added directly to the
samples written to the I DAC.
0
I DAC Offset MSB 0x3D [7:0] I DAC offset[15:8] See Register 0x3C. 0
Q DAC Offset LSB 0x3E [7:0] Q DAC offset[7:0]
Q DAC offset[15:0] is a value added directly to the
samples written to the Q DAC.
0
Q DAC Offset MSB 0x3F [7:0] Q DAC offset[15:8] See Register 0x3E. 0
I DAC FS Adjust 0x40 [7:0] I DAC FS adjust[7:0]
I DAC FS adjust[9:0] sets the full-scale current of the
I DAC. The full-scale current can be adjusted from 8.64 mA
to 31.6 mA in step sizes of approximately 22.5 μA.
F9
0x000 = 8.64 mA.
…
0x200 = 20.14 mA.
…
0x3FF = 31.66 mA.
I DAC Control 0x41 7 I DAC sleep
1 = puts the I-channel DAC into sleep mode (fast wake-
up mode).
0
[1:0] I DAC FS adjust[9:8] See Register 0x40. 1
Aux DAC I Data 0x42 [7:0] I aux DAC[7:0]
I aux DAC[9:0] sets the magnitude of the auxiliary DAC
current. The range is 0 mA to 2 mA, and the step size is 2 μA.
0
0x000 = 0.000 mA.
0x001 = 0.002 mA.
…
0x3FF = 2.046 mA.