Datasheet

AD9125
Rev. 0 | Page 24 of 56
Register
Name
Address
(Hex) Bits Name Description Default
110 = 64.
111 = 128.
Sync Control 2 0x11 5:0 Sync phase request[5:0]
This sets the requested clock phase offset after sync.
The offset unit is in DACCLK cycles. This enables
repositioning of the DAC output with respect to the
sync input. The offset can also be used to skew the DAC
outputs between the synchronized DACs.
0
000000 = 0 DACCLK cycles.
000001 = 1 DACCLK cycle.
…
111111 = 63 DACCLK cycles.
Sync Status 1 0x12 7 Sync lost
1 = indicates that synchronization had been attained
but was subsequently lost.
R
6 Sync locked 1 = indicates that synchronization has been attained. R
Sync Status 2 0x13 [7:0] Sync phase readback[7:0]
Indicates the averaged sync phase offset (6.2 format). If
the value differs from the requested sync phase value,
this indicates sync timing errors.
R
00000000 = 0.0.
00000001 = 0.25.
…
11111110 = 63.50.
11111111 = 63.75.
FIFO Control 0x17 [2:0] FIFO phase offset[2:0]
FIFO write pointer phase offset following FIFO reset.
This is the difference between the read pointer and the
write pointer values upon FIFO reset. The optimal value
is nominally 4.
4
000 = 0.
001 = 1.
…
111 = 7.
FIFO Status 1 0x18 7 FIFO Warning 1 FIFO read and write pointers within ±1. 0
6 FIFO Warning 2 FIFO read and write pointers within ±2. 0
2
FIFO soft align
acknowledge
FIFO read and write pointers are aligned after a serial
port initiated FIFO reset.
1 FIFO soft align request
Request FIFO read and write pointers alignment via the
serial port.
0
0 FIFO reset aligned
FIFO read and write pointers aligned after a hardware
reset.
0
FIFO Status 2 0x19 [7:0] FIFO level[7:0] Thermometer encoded measure of the FIFO level. 0
Datapath Control 0x1B 7 Bypass premod 1 = bypasses f
S
/2 premodulator. 1
6 Bypass sinc
−1
1 = bypasses inverse sinc filter. 1
5 Bypass NCO 1 = bypasses NCO. 1
3 NCO gain
0 = default. No gain scaling is applied to the NCO input
to the internal digital modulator.
0
1 = gain scaling of 0.5 is applied to the NCO input to the
internal digital modulator. This can eliminate saturation
of the modulator output for some combinations of data
inputs and NCO signals.
2
Bypass phase compen-
sation and dc offset
1 = bypasses phase compensation and dc offset. 1