Datasheet

AD9125
Rev. 0 | Page 23 of 56
Register
Name
Address
(Hex) Bits Name Description Default
PLL Control 1 0x0A 7 PLL enable
1 = enables the PLL clock multiplier. REFCLK input is
used as the PLL reference clock signal.
0
6 PLL manual enable Enables the manual selection of the VCO band. 1
1 = manual mode; the correct VCO band must be
determined by the user.
[5:0] Manual VCO band Selects the VCO band to be used. 0
PLL Control 2 0x0C [7:5]
PLL loop
bandwidth[2:0]
Selects the PLL loop filter bandwidth. 110
000 = loop bandwidth is nominally 200 kHz
010 = loop bandwidth is nominally 450 kHz
100 = loop bandwidth is nominally 950 kHz
110 = loop bandwidth is nominally 2 MHz
[4:0]
PLL charge pump
current[4:0]
Sets the nominal PLL charge-pump current. 10001
00000 = lowest current setting.
11111 = highest current setting.
PLL Control 3 0x0D [7:6] N2[1:0]
PLL control clock divider. These bits determine the ratio
of the DACCLK rate to the PLL controller clock rate.
f
PC_CLK
must always be less than 80 MHz.
3
00 = f
DACCLK
/f
PC_CLK
= 2.
01 = f
DACCLK
/f
PC_CLK
= 4.
10 = f
DACCLK
/f
PC_CLK
= 8.
11 = f
DACCLK
/f
PC_CLK
= 16.
4 PLL cross control enable Enables PLL cross-point controller. 1
[3:2] N0[1:0]
PLL VCO divider. These bits determine the ratio of the
VCO output to the DACCLK frequencies.
10
00 = f
VCO
/f
DACCLK
= 1.
01 = f
VCO
/f
DACCLK
= 2.
10 = f
VCO
/f
DACCLK
= 4.
11 = f
VCO
/f
DACCLK
= 4.
[1:0] N1[1:0]
PLL loop divider. These bits determine the ratio of the
DACCLK to the REFCLK frequencies.
01
00 = f
DACCLK
/f
REFCLK
= 2.
01 = f
DACCLK
/f
REFCLK
= 4.
10 = f
DACCLK
/f
REFCLK
= 8.
11 = f
DACCLK
/f
REFCLK
= 16.
PLL Status 1 0x0E 7 PLL lock
The PLL generated clock is tracking the REFCLK input
signal.
R
[3:0]
VCO control
voltage[3:0]
VCO control voltage readback (see Table 25). R
PLL Status 2 0x0F [5:0]
VCO band
readback[5:0]
Indicates the VCO band currently selected. R
Sync Control 1 0x10 7 Sync enable 1 = enables the synchronization logic. 0
6 Data/FIFO rate toggle 0 = operates the synchronization at the FIFO reset rate. 1
1 = operates the synchronization at the data rate.
3 Rising edge sync 0 = sync is initiated on the falling edge of the sync input. 1
1 = sync is initiated on the rising edge of the sync input.
[2:0] Sync averaging[2:0]
Sets the number of input samples that are averaged for
determining the sync phase.
0
000 = 1.
001 = 2.
010 = 4.
011 = 8.
100 = 16.
101 = 32.