Datasheet

AD9125
Rev. 0 | Page 22 of 56
Register
Name
Address
(Hex) Bits Name Description Default
1 Enable FIFO Warning 1 1 = enables interrupt for FIFO Warning 1. 0
0 Enable FIFO Warning 2 1 = enables interrupt for FIFO Warning 2. 0
Interrupt Enable 2 0x05 7 Set to 0 Set this bit to 0. 0
6 Set to 0 Set this bit to 0. 0
5 Set to 0 Set this bit to 0. 0
4
Enable AED comparison
pass
1 = enables interrupt for AED comparison pass. 0
3
Enable AED comparison
fail
1 = enables interrupt for AED comparison fail. 0
2
Enable SED comparison
fail
1 = enables interrupt for SED comparison fail. 0
1 Set to 0 Set this bit to 0. 0
0 Set to 0 Set this bit to 0. 0
Event Flag 1
1
0x06 7 PLL lock lost
1 = indicates that the PLL, which had been previously
locked, has unlocked from the reference signal. This is a
latched signal.
0
6 PLL locked
1 = indicates that the PLL has locked to the reference
clock input.
0
5 Sync signal lost
1 = indicates that the sync logic, which had been
previously locked, has lost alignment. This is a latched
signal.
0
4 Sync signal locked
1 = indicates that the sync logic did achieve sync
alignment. This is indicated when no phase changes
were requested for at least a few full averaging cycles.
0
3 Sync phase locked
1 = indicates that the internal digital clock generation logic
is ready. This occurs when internal clocks are present and
stable.
0
2 Soft FIFO sync
1 = indicates that a FIFO reset originating from a serial
port-based request has successfully completed. This is a
latched signal.
0
1 FIFO Warning 1
1 = indicates that the difference between the FIFO read
and write pointers is 1.
0
0 FIFO Warning 2
1 = indicates that the difference between the FIFO read
and write pointers is 2.
0
Event Flag 2
1
0x07 4 AED comparison pass
1 = indicates that the SED logic detected a valid input
data pattern compared with the preprogrammed
expected values. This is a latched signal.
0
3 AED comparison fail
1 = indicates that the SED logic detected an invalid
input data pattern compared with the preprogrammed
expected values. This is a latched signal that auto-
matically clears when eight valid I/Q data pairs are
received.
0
2 SED comparison fail
1 = indicates that the SED logic detected an invalid
input data pattern compared with the preprogrammed
expected values. This is a latched signal.
Clock Receiver
Control
0x08 7 DACCLK duty correction 1 = enables duty-cycle correction on the DACCLK input. 0
6 REFCLK duty correction 1 = enables duty-cycle correction on the REFCLK input. 0
5 DACCLK cross-correction
1 = enables differential crossing correction on the DACCLK
input.
1
4 REFCLK cross-correction
1 = enables differential crossing correction on the
REFCLK input.
1