Datasheet

AD9125
Rev. 0 | Page 18 of 56
SERIAL PORT OPTIONS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by the LSB_FIRST bit
(Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0).
When LSB_FIRST = 0 (MSB-first), the instruction and data bit
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent data
bytes should follow from the high address to the low address. In
MSB-first mode, the serial port internal byte address generator
decrements for each data byte of the multibyte communi-
cation cycle.
When LSB_FIRST = 1 (LSB-first), the instruction and data bit
must be written from LSB to MSB. Multibyte data transfers in
LSB-first format start with an instruction byte that includes the
register address of the least significant data byte followed by
multiple data bytes. The serial port internal byte address generator
increments for each byte of the multibyte communication cycle.
The serial port controller data address decrements from the
data address written toward 0x00 for multibyte I/O operations
if the MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x7F for
multibyte I/O operations if the LSB-first mode is active.
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CS
SCLK
SDIO
SDO
09016-011
Figure 38. Serial Register Interface Timing, MSB First
SCLK
SDIO
SDO
CS
A0 A1 A2 A3 A4 N0 N1 R/W D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
INSTRUCTION CYCLE DATA TRANSFER CYCLE
09016-012
Figure 39. Serial Register Interface Timing, LSB First
SCLK
SDIO
CS
INSTRUCTION BIT 6INSTRUCTION BIT 7
t
DS
t
DS
t
DH
t
PWH
t
PWL
t
SCLK
09016-013
Figure 40. Timing Diagram for Serial Port Register Write (t
DS
to t
D
CS
)
SCLK
SDIO,
SDO
CS
DATA BIT n – 1DATA BIT n
t
DV
09016-014
Figure 41. Timing Diagram for Serial Port Register Read