Datasheet

AD9122
Rev. B | Page 59 of 60
EXAMPLE START-UP ROUTINE
To ensure reliable start-up of the AD9122, certain sequences
should be followed. This section shows an example start-up
routine. This example uses the configuration described in the
Device Configuration section.
DEVICE CONFIGURATION
The following device configuration is used for this example:
• f
DATA
= 122.88 MSPS
• Interpolation is 4×, using HB1 = 10 and HB2 = 010010
• Input data is baseband data
• f
OUT
= 140 MHz
• f
REFCLK
= 122.88 MHz
• PLL is enabled
• Fine NCO is enabled
• Inverse sinc filter is enabled
• Synchronization is enabled
• Silicon revision is R2
DERIVED PLL SETTINGS
The following PLL settings can be derived from the device
configuration:
• f
DACCLK
= f
DATA
× interpolation = 491.52 MHz
• f
VCO
= 4 × f
DACCLK
= 1966.08 MHz (1 GHz < f
VCO
< 2 GHz)
• N1 = f
DACCLK
/f
REFCLK
= 4
• N2 = f
VCO
/f
DACCLK
= 4
DERIVED NCO SETTINGS
The following NCO settings can be derived from the device
configuration:
• f
NCO
= 2 × f
DATA
• f
CARRIER
= f
OUT
− f
MODHB1
= 140 − 122.88 = 17.12 MHz
• FTW = 17.12/(2 × 122.8) × 2
32
= 0x11D55555
START-UP SEQUENCE
The following sequence configures the power clock and register
write sequencing for reliable device start-up in PLL ON mode:
Power up Device (no specific power supply
sequence is required)
Apply stable REFCLK input signal.
Apply stable DCI input signal.
Issue H/W RESET (Optional).
Device Configuration Register Write Sequence:
0x00 Æ 0x20 /* Issue Software Reset */
0x00 Æ 0x00
/* Start PLL */
0x0D Æ 0xD9
0x0A Æ 0xC0
0x0A Æ 0x80
/* Verify PLL is Locked */
Read 0x0E /* Expect bit 7 = 1 */
/* Configure Interpolation Filters */
0x1B Æ 0x84
0x1C Æ 0x04
0x1D Æ 0x24
/* Configure NCO */
0x1E Æ 0x01
0x30 Æ 0x55
0x31 Æ 0x55
0x32 Æ 0xD5
0x33 Æ 0x11
/* Update Frequency Tuning Word */
0x36 Æ 0x01
0x36 Æ 0x00
/* Choose Data Rate Mode */
0x10 Æ 0x48
/* Issue Software FIFO Reset */
0x17 Æ 0x04
0x18 Æ 0x02
/* Verify FIFO Reset */
Read 0x18 /* Expect 0x07 */
0x18 Æ 0x00
Read 0x19 /* Expect 0x1F or 0x0F or 0x07 */