Datasheet

AD9122
Rev. B | Page 57 of 60
INTERFACE TIMING VALIDATION
The AD9122 provides on-chip sample error detection (SED)
circuitry that simplifies verification of the input data interface.
The SED circuitry compares the input data samples captured
at the digital input pins with a set of comparison values. The
comparison values are loaded into registers through the SPI
port. Differences between the captured values and the compar-
ison values are detected and stored. Options are available for
customizing SED test sequencing and error handling.
SED OPERATION
The SED circuitry operates on a data set made up of four 16-bit
input words, denoted as I0, Q0, I1, and Q1. To properly align
the input samples, the first I data-word (that is, I0) is indicated
by asserting FRAME for at least one complete input sample.
Figure 88 shows the input timing of the interface in word mode.
The FRAME signal can be issued once at the start of the data
transmission, or it can be asserted repeatedly at intervals coinciding
with the I0 and Q0 data-words.
FRAME
DATA[15:0] Q1Q0I0 I1 I0 Q0
08281-056
Figure 88. Timing Diagram of Extended FRAME Signal Required
to Align Input Data for SED
The SED has three flag bits (Register 0x67, Bit 5, Bit 1, and Bit 0)
that indicate the results of the input sample comparisons. The
sample error detected bit (Register 0x67, Bit 5) is set when an
error is detected and remains set until cleared. The SED also
provides registers that indicate which input data bits experienced
errors (Register 0x70 through Register 0x73). These bits are
latched and indicate the accumulated errors detected until cleared.
Autosample error detection (AED) is an autoclear function in
the SED. The autoclear mode has two effects: it activates the
compare fail bit and the compare pass bit (Register 0x67, Bit 1
and Bit 0) and changes the behavior of Register 0x70 through
Register 0x73. The compare pass bit is set if the last comparison
indicated that the sample was error free. The compare fail bit is
set if an error is detected. The compare fail bit is automatically
cleared by the reception of eight consecutive error-free compar-
isons. When autoclear mode is enabled, Register 0x70 through
Register 0x73 accumulate errors as previously described but are
reset to all 0s after eight consecutive error-free sample comparisons
are made.
If desired, the sample error detected, compare pass, and com-
pare fail flags can be configured to trigger the
IRQ
pin when
active. This is done by enabling the appropriate bits in the event
flag register (Register 0x07).
Table 2 7 shows a progression of the input sample comparison
results and the corresponding states of the error flags.
Table 27. Progression of Input Sample Comparison Results and the Resulting SED Register Values
Compare Results (Pass/Fail) P F F F P P P P P P P P P F P F
Register 0x67, Bit 5 (Sample Error Detected) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Register 0x67, Bit 1 (Compare Fail) 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
Register 0x67, Bit 0 (Compare Pass) 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1
0
Register 0x70 to Register 0x73
(Errors Detected x_BITS[15:0])
Z
1
N
2
N
2
N
2
N
2
N
2
N
2
N
2
N
2
N
2
N
2
N
2
Z
1
N
2
N
2
N
2
1
Z = all 0s.
2
N = nonzero.