Datasheet

AD9122
Rev. B | Page 56 of 60
INTERRUPT REQUEST OPERATION
The AD9122 provides an interrupt request output signal on
Pin 7 (
IRQ
) that can be used to notify an external host processor
of significant device events. Upon assertion of the interrupt, the
device should be queried to determine the precise event that
occurred. The
IRQ
pin is an open-drain, active low output. Pull
the
IRQ
pin high external to the device. This pin can be tied to
the interrupt pins of other devices with open-drain outputs to
wire-OR these pins together.
The event flags provide visibility into the device. These flags
are located in the two event flag registers, Register 0x06 and
Register 0x07. The behavior of each event flag is independently
selected in the interrupt enable registers, Register 0x04 and
Register 0x05. When the flag interrupt enable is active, the event
flag latches and triggers an external interrupt. When the flag
interrupt is disabled, the event flag monitors the source signal,
but the
IRQ
pin remains inactive.
Figure 87 shows the
IRQ
-related circuitry and how the event flag
signals propagate to the
IRQ
output. The INTERRUPT_ENABLE
signal represents one bit from the interrupt enable register. The
EVENT_FLAG_SOURCE signal represents one bit from the event
flag register. The EVENT_FLAG_SOURCE signal represents
one of the device signals that can be monitored, such as the
PLL_LOCKED signal from the PLL phase detector or the
FIFO_WARNING_1 signal from the FIFO controller.
When an interrupt enable bit is set high, the corresponding
event flag bit reflects a positively tripped version of the
EVENT_FLAG_SOURCE signal; that is, the event flag bit is
latched on the rising edge of the EVENT_FLAG_SOURCE
signal. This signal also asserts the external
IRQ
pin.
When an interrupt enable bit is set low, the event flag bit reflects
the current status of the EVENT_FLAG_SOURCE signal, and
the event flag has no effect on the external
IRQ
pin.
The latched version of an event flag (the INTERRUPT_SOURCE
signal) can be cleared in two ways. The recommended way is by
writing 1 to the corresponding event flag bit. A hardware or soft-
ware reset also clears the INTERRUPT_SOURCE signal.
INTERRUPT SERVICE ROUTINE
Interrupt request management starts by selecting the set of
event flags that require host intervention or monitoring. The
events that require host action should be enabled so that the
host is notified when they occur. For events requiring host
intervention upon
IRQ
activation, run the following routine
to clear an interrupt request:
1.
Read the status of the event flag bits that are being
monitored.
2.
Set the interrupt enable bit low so that the unlatched
EVENT_FLAG_SOURCE signal can be monitored directly.
3.
Perform any actions that may be required to clear the
EVENT_FLAG_SOURCE. In many cases, no specific
actions may be required.
4.
Read the event flag to verify that the actions taken have
cleared the EVENT_FLAG_SOURCE.
5.
Clear the interrupt by writing 1 to the event flag bit.
6.
Set the interrupt enable bits of the events to be monitored.
Note that some EVENT_FLAG_SOURCE signals are latched
signals. These signals are cleared by writing to the correspond-
ing event flag bit. For more information about each event flag,
see Register 0x06 and Register 0x07 in Table 11.
INTERRUPT_ENABLE
EVENT_FLAG_SOURCE
DEVICE_RESET
EVENT_FLAG
INTERRUPT_
SOURCE
1
0
OTHER
INTERRUPT
SOURCES
IRQ
WRITE_1_TO_EVENT_FLAG
08281-054
Figure 87. Simplified Schematic of
IRQ
Circuitry