Datasheet

AD9122
Rev. B | Page 53 of 60
REFCLKP(1)/
REFCLKN(1)
REFCLKP(2)/
REFCLKN(2)
DCIP(2)/
DCIN(2)
FRAMEP(2)/
FRAMEN(2)
t
SKEW
t
SDCI
t
HDCI
08281-050
Figure 82. Timing Diagram Required for Synchronizing Devices
DACCLKP/
DACCLKN
FRAMEP/
FRAMEN
REFCLKP/
REFCLKN
DCIP/
DCIN
IOUT1P/
IOUT1N
DCIP/
DCIN
DACCLKP/
DACCLKN
REFCLKP/
REFCLKN
FRAMEP/
FRAMEN
IOUT2P/
IOUT2N
SAMPLE
RATE CLOCK
LOW SKEW
CLOCK DRIVER
SYNC
CLOCK
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
FPGA
08281-051
Figure 83. Typical Circuit Diagram for Synchronizing Devices to a System Clock
To maintain synchronization, the skew between the REFCLK
signals of the devices must be less than t
SKEW
ns. When resetting
the FIFO, the FRAME signal must be held high for the time
interval required to write two complete input data words. A
timing diagram of the input signals is shown in Figure 82.
Figure 82 shows a REFCLK frequency equal to the data rate.
Although this is the most common situation, it is not strictly
required for proper synchronization. Any REFCLK frequency
that satisfies the following equation is acceptable. (This
equation is valid only when the PLL is used because only data
rate mode is available with the PLL on.)
f
SYNC_I
= f
DACCLK
/2
N
and f
SYNC_I
≤ f
DATA
where N = 0, 1, 2, or 3.
As an example, a configuration with 4× interpolation and clock
frequencies of f
VCO
= 1600 MHz, f
DACCLK
= 800 MHz, f
DATA
=
200 MHz, and f
SYNC_I
= 100 MHz is a viable solution.
SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock, a separate
REFCLK input signal is required for synchronization. To syn-
chronize devices, the DACCLK signal and the REFCLK signal
must be distributed with low skew to all the devices being
synchronized. If the devices need to be synchronized to a
master clock, use the master clock directly for generating the
REFCLK input (see Figure 83).
DATA RATE MODE SYNCHRONIZATION
The Procedure for Data Rate Synchronization When Directly
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in data rate mode. The
procedure assumes that the DACCLK and REFCLK signals are
applied to all the devices. The following procedure must be
carried out on each individual device.
Procedure for Data Rate Synchronization When Directly
Sourcing the DAC Sampling Clock
Configure the AD9122 for data rate, periodic synchronization
by writing 0xC8 to the sync control register (Register 0x10).
Additional synchronization options are available (see the
Additional Synchronization Features section).
Read the sync locked bit (Register 0x12, Bit 6) to verify that the
device is back-end synchronized. A high level on this bit indicates
that the clocks are running with a constant and known phase
relative to the synchronization signal.
Reset the FIFO by strobing the FRAME signal high for one
complete DCI period. Resetting the FIFO ensures that the
correct data is being read from the FIFO of each of the devices
simultaneously.