Datasheet

AD9122
Rev. B | Page 33 of 60
The setup (t
S
) and hold (t
H
) times, with respect to the edges,
are shown in Figure 46. The minimum setup and hold times
are shown in Table 13 .
08281-146
DCI
DAT
A
t
DATA
t
DATA
SAMPLING
INTERVAL
SAMPLING
INTERVAL
t
S
t
S
t
H
t
H
Figure 46. Timing Diagram for Input Data Port
Table 13. Data to DCI Setup and Hold Times
DCI Delay
Register 0x16,
Bits[1:0]
Minimum Setup
Time, t
S
(ns)
Minimum Hold
Time, t
H
(ns)
Sampling
Interval (ns)
00 −0.05 0.65 0.6
01 −0.23 0.95 0.72
10 −0.38 1.22 0.84
11 −0.47 1.38 0.91
The data interface timing can be verified by using the sample
error detection (SED) circuitry. See the Interface Timing
Va li d at io n section for more information.
FIFO OPERATION
The AD9122 contains a 2-channel, 16-bit wide, eight-word deep
FIFO designed to relax the timing relationship between the data
arriving at the DAC input ports and the internal DAC data rate
clock. The FIFO acts as a buffer that absorbs timing variations
between the data source and the DAC, such as the clock-to-data
variation of an FPGA or ASIC, which significantly increases the
timing budget of the interface.
Figure 47 shows the block diagram of the datapath through
the FIFO. The data is latched into the device, is formatted, and
is then written into the FIFO register determined by the FIFO
write pointer. The value of the write pointer is incremented
every time a new word is loaded into the FIFO. Meanwhile, data
is read from the FIFO register determined by the read pointer
and fed into the digital datapath. The value of the read pointer
is incremented every time data is read into the datapath from
the FIFO. The FIFO pointers are incremented at the data rate
(DACCLK rate divided by the interpolation ratio).
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow or become empty. An overflow or empty
condition of the FIFO occurs when the write pointer and read
pointer point to the same FIFO location. This simultaneous
access of data leads to unreliable data transfer through the FIFO
and must be avoided.
Nominally, data is written to and read from the FIFO at the same
rate. This keeps the FIFO depth constant. If data is written to
the FIFO faster than data is read out, the FIFO depth increases.
If data is read out of the FIFO faster than data is written to it,
the FIFO depth decreases. For optimum timing margin, the
FIFO depth should be maintained near half full (a difference of
4 between the write pointer and read pointer values). The FIFO
depth represents the FIFO pipeline delay and is part of the over-
all latency of the AD9122.
I AND Q
DACS
323232
32 BITS
÷ INT
DCI
DACCLK
DATA
I AND Q
DATA
PATHS
DATA
FORMAT
INPUT
LATCH
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
08281-018
RESET
LOGIC
FRAME
SYNC
FIFO SOFT ALIGN REQUEST
REG 0x18[1]
DATA/FIFO RATE
REG 0x10[6]
FIFO PHASE OFFSET
REG 0x17[2:0]
READ POINTER RESET WRITE POINTER RESET
READ
POINTER
WRITE
POINTER
Figure 47. Block Diagram of FIFO