Datasheet

AD9122
Rev. B | Page 32 of 60
LVDS INPUT DATA PORTS
The AD9122 has one LVDS data port that receives data for
both the I and Q transmit paths. The device can accept data in
word, byte, and nibble formats. In word, byte, and nibble modes,
the data is sent over 16-bit, 8-bit, and 4-bit LVDS data buses,
respectively. The pin assignments of the bus in each mode are
shown in Table 12.
Table 12. Data Bit Pair Assignments for Data Input Modes
Mode MSB to LSB
Word D15, D14, …, D0
Byte
1
D14, D12, D10, D8, D7, D5, D3, D1
Nibble
1
D10, D8, D7, D5
1
In byte and nibble modes, the unused pins can be left floating.
The data is accompanied by a reference bit (DCI) that is used
to generate a double data rate (DDR) clock. In byte and nibble
modes, a FRAME signal is required for controlling to which DAC
the data is sent. All of the interface signals are time aligned, so
there is a maximum skew requirement on the bus.
WORD INTERFACE MODE
In word mode, the DCI signal is a reference bit used to generate
the data sampling clock. The DCI signal should be time aligned
with the data. The I DAC data should correspond to DCI high,
and the Q DAC data should correspond to DCI low, as shown
in Figure 43.
DCI
Q
0
I
1
Q
1
I
2
Q
2
I
3
Q
3
DATA[15:0]
08281-015
Figure 43. Timing Diagram for Word Mode
BYTE INTERFACE MODE
In byte mode, the DCI signal is a reference bit used to generate
the data sampling clock. The DCI signal should be time aligned
with the data. The most significant byte of the data should corre-
spond to DCI high, and the least significant byte of the data should
correspond to DCI low. The FRAME signal indicates to which
DAC the data is sent. When FRAME is high, data is sent to the
I DAC; when FRAME is low, data is sent to the Q DAC. The
complete timing diagram is shown in Figure 44.
NIBBLE INTERFACE MODE
In nibble mode, the DCI signal is a reference bit used to generate
the data sampling clock. The DCI signal should be time aligned
with the data. The FRAME signal indicates to which DAC the
data is sent. When FRAME is high, data is sent to the I DAC;
when FRAME is low, data is sent to the Q DAC. All four nibbles
must be written to the device for proper operation. For 12-bit
resolution devices, the data in the fourth nibble acts as a place-
holder for the data framing structure. The complete timing
diagram is shown in Figure 45.
INTERFACE TIMING
The timing diagram for the digital interface port is shown in
Figure 46. The sampling point of the data bus nominally occurs
350 ps after each edge of the DCI signal and has an uncertainty
of ±300 ps, as illustrated by the sampling interval shown in
Figure 46. The data and FRAME signals must be valid through-
out this sampling interval. The data and FRAME signals may
change at any time between sampling intervals.
DCI
DATA[15:0]
FRAME
Q
0LSB
I
1MSB
I
1LSB
Q
1MSB
Q
1LSB
I
2MSB
I
2LSB
Q
2MSB
Q
2LSB
08281-016
Figure 44. Timing Diagram for Byte Mode
DCI
DATA[15:0]
FRAME
Q
0N0
I
1N3
I
1N2
I
1N1
I
1N0
Q
1N3
Q
1N2
Q
1N1
Q
1N0
I
2N3
0
8281-017
Figure 45. Timing Diagram for Nibble Mode