Datasheet

AD9122
Rev. B | Page 28 of 60
Register
Name
Address
(Hex) Bits Name Description Default
HB3 Control 0x1E [6:1] HB3[5:0] Modulation mode for I Side Half-Band Filter 3. 000000
000000 = input signal not modulated; filter pass band is
from −0.2 to +0.2 of f
IN3
.
001001 = input signal not modulated; filter pass band is
from 0.05 to 0.45 of f
IN3
.
010010 = input signal not modulated; filter pass band is
from 0.3 to 0.7 of f
IN3
.
011011 = input signal not modulated; filter pass band is
from 0.55 to 0.95 of f
IN3
.
100100 = input signal modulated by f
IN3
; filter pass band is
from 0.8 to 1.2 of f
IN3
.
101101 = input signal modulated by f
IN3
; filter pass band is
from 1.05 to 1.45 of f
IN3
.
110110 = input signal modulated by f
IN3
; filter pass band is
from 1.3 to 1.7 of f
IN3
.
111111 = input signal modulated by f
IN3
; filter pass band is
from 1.55 to 1.95 of f
IN3
.
0 Bypass HB3 1 = bypass the third-stage interpolation filter. 0
Chip ID 0x1F [7:0] Chip ID[7:0] This register identifies the device as an AD9122. 00001000
FTW LSB 0x30 [7:0] FTW[7:0] See Register 0x33. 00000000
FTW 0x31 [7:0] FTW[15:8] See Register 0x33. 00000000
FTW 0x32 [7:0] FTW[23:16] See Register 0x33. 00000000
FTW MSB 0x33 [7:0] FTW[31:24]
FTW[31:0] is the 32-bit frequency tuning word that deter-
mines the frequency of the complex carrier generated by the
on-chip NCO. The frequency is not updated when the FTW
registers are written. The values are only updated when Bit 0
of Register 0x36 transitions from 0 to 1.
00000000
NCO Phase
Offset LSB
0x34 [7:0] NCO Phase Offset[7:0] See Register 0x35. 00000000
NCO Phase
Offset MSB
0x35 [7:0] NCO Phase Offset[15:8]
The NCO sets the phase of the complex carrier signal when
the NCO is reset. The phase offset spans from 0° to 360°.
Each bit represents an offset of 0.0055°. This value is in
twos complement format.
00000000
NCO FTW
Update
0x36 5 FRAME FTW acknowledge
1 = the NCO has been reset due to an extended FRAME
pulse signal.
0
4 FRAME FTW request
0 = the NCO is reset on the first extended FRAME pulse after
this bit is set to 1.
0
1 Update FTW acknowledge 1 = the FTW has been updated. 0
0 Update FTW request The FTW is updated on the 0-to-1 transition of this bit. 0
I Phase Adj
LSB
0x38 [7:0] I Phase Adj[7:0] See Register 0x39. 00000000
I Phase Adj
MSB
0x39 [1:0] I Phase Adj[9:8]
I Phase Adj[9:0] is used to insert a phase offset between
the I and Q datapaths. This offset can be used to correct
for phase imbalance in a quadrature modulator. See the
Quadrature Phase Correction section for more information.
00
Q Phase Adj
LSB
0x3A [7:0] Q Phase Adj[7:0] See Register 0x3B. 00000000
Q Phase Adj
MSB
0x3B [1:0] Q Phase Adj[9:8]
Q Phase Adj[9:0] is used to insert a phase offset between
the I and Q datapaths. This offset can be used to correct
for phase imbalance in a quadrature modulator. See the
Quadrature Phase Correction section for more information.
00
I DAC Offset
LSB
0x3C [7:0] I DAC Offset[7:0] See Register 0x3D. 00000000
I DAC Offset
MSB
0x3D [7:0] I DAC Offset[15:8]
I DAC Offset[15:0] is a value that is added directly to the
samples written to the I DAC.
00000000