Datasheet
AD9122
Rev. B | Page 25 of 60
Register
Name
Address
(Hex) Bits Name Description Default
PLL Control 0x0D [7:6] N2[1:0]
PLL control clock divider. This divider determines the ratio of
the DACCLK frequency to the PLL controller clock frequency.
f
PC_CLK
must always be less than 75 MHz.
11
00 = f
DACCLK
/f
PC_CLK
= 2.
01 = f
DACCLK
/f
PC_CLK
= 4.
10 = f
DACCLK
/f
PC_CLK
= 8.
11 = f
DACCLK
/f
PC_CLK
= 16.
4 PLL cross-control enable 1 = enable PLL cross-point controller. 1
[3:2] N0[1:0]
PLL VCO divider. This divider determines the ratio of the VCO
frequency to the DACCLK frequency.
10
00 = f
VCO
/f
DACCLK
= 1.
01 = f
VCO
/f
DACCLK
= 2.
10 = f
VCO
/f
DACCLK
= 4.
11 = f
VCO
/f
DACCLK
= 4.
[1:0] N1[1:0]
PLL loop divider. This divider determines the ratio of the
DACCLK frequency to the REFCLK frequency.
01
00 = f
DACCLK
/f
REFCLK
= 2.
01 = f
DACCLK
/f
REFCLK
= 4.
10 = f
DACCLK
/f
REFCLK
= 8.
11 = f
DACCLK
/f
REFCLK
= 16.
PLL Status 0x0E 7 PLL locked
1 = the PLL-generated clock is tracking the REFCLK input
signal.
N/A
[3:0] VCO Control Voltage[3:0] VCO control voltage readback. See Table 24. N/A
0x0F [5:0] VCO Band Readback[5:0] Indicates the VCO band currently selected. N/A
Sync
Control
0x10 7 Sync enable 1 = enable the synchronization logic. 0
6 Data/FIFO rate toggle 0 = operate the synchronization at the FIFO reset rate. 1
1 = operate the synchronization at the data rate.
3 Rising edge sync 0 = sync is initiated on the falling edge of the sync input. 1
1 = sync is initiated on the rising edge of the sync input.
[2:0] Sync Averaging[2:0]
Sets the number of input samples that are averaged in
determining the sync phase.
000
000 = 1.
001 = 2.
010 = 4.
011 = 8.
100 = 16.
101 = 32.
110 = 64.
111 = 128.
0x11 [5:0] Sync Phase Request[5:0]
This register sets the requested clock phase offset after sync.
The offset unit is in DACCLK cycles. This register enables
repositioning of the DAC output with respect to the sync
input. The offset can also be used to skew the DAC outputs
between the synchronized DACs.
000000
000000 = 0 DACCLK cycles.
000001 = 1 DACCLK cycle.
…
111111 = 63 DACCLK cycles.