Datasheet

AD9122
Rev. B | Page 24 of 60
Register
Name
Address
(Hex) Bits Name Description Default
Interrupt
Enable
0x05 [7:5] Set to 0 Set these bits to 0. 000
4 Enable AED compare pass 1 = enable interrupt for AED comparison pass. 0
3 Enable AED compare fail 1 = enable interrupt for AED comparison fail. 0
2 Enable SED compare fail 1 = enable interrupt for SED comparison fail. 0
[1:0] Set to 0 Set these bits to 0. 00
Event Flag 0x06 7 PLL lock lost
1 = indicates that the PLL, which had been previously
locked, has unlocked from the reference signal. This is a
latched signal.
N/A
6 PLL locked
1 = indicates that the PLL has locked to the reference
clock input.
N/A
5 Sync signal lost
1 = indicates that the sync logic, which had been previously
locked, has lost alignment. This is a latched signal.
N/A
4 Sync signal locked
1 = indicates that the sync logic has achieved sync
alignment. This is indicated when no phase changes
were requested for at least a few full averaging cycles.
N/A
1 FIFO Warning 1
1 = indicates that the difference between the FIFO read
and write pointers is 1.
N/A
0 FIFO Warning 2
1 = indicates that the difference between the FIFO read
and write pointers is 2.
N/A
Note that all event flags are cleared by writing the respective bit high.
0x07 4 AED compare pass
1 = indicates that the SED logic detected a valid input data
pattern compared against the preprogrammed expected
values. This is a latched signal.
N/A
3 AED compare fail
1 = indicates that the SED logic detected an invalid input
data pattern compared against the preprogrammed
expected values. This latched signal is automatically cleared
when eight valid I/Q data pairs are received.
N/A
2 SED compare fail
1 = indicates that the SED logic detected an invalid input
data pattern compared against the preprogrammed
expected values. This is a latched signal.
N/A
Note that all event flags are cleared by writing the respective bit high.
Clock
Receiver
Control
0x08 7 DACCLK duty correction 1 = enable duty cycle correction on the DACCLK input. 0
6 REFCLK duty correction 1 = enable duty cycle correction on the REFCLK input. 0
5 DACCLK cross-correction
1 = enable differential crossing correction on the DACCLK
input.
1
4 REFCLK cross-correction
1 = enable differential crossing correction on the REFCLK
input.
1
PLL Control 0x0A 7 PLL enable
1 = enable the PLL clock multiplier. The REFCLK input is used
as the PLL reference clock signal.
0
6 PLL manual enable
1 = enable manual selection of the VCO band. The correct
VCO band must be determined by the user and written to
Bits[5:0].
1
[5:0] Manual VCO Band[5:0] Selects the VCO band to be used. 000000
0x0C [7:6] PLL Loop Bandwidth[1:0] Selects the PLL loop filter bandwidth. 11
00 = widest bandwidth.
…
11 = narrowest bandwidth.
[4:0]
PLL Charge Pump
Current[4:0]
Sets the nominal PLL charge pump current. 10001
00000 = lowest current setting.
…
11111 = highest current setting.