Datasheet

AD9122
Rev. B | Page 22 of 60
Addr
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default
0x1C HB1 control HB1[1:0] Bypass HB1 0x00
0x1D HB2 control HB2[5:0] Bypass HB2 0x00
0x1E HB3 control HB3[5:0] Bypass HB3 0x00
0x1F Chip ID Chip ID[7:0] 0x08
0x30 FTW LSB FTW[7:0] 0x00
0x31 FTW FTW[15:8] 0x00
0x32 FTW FTW[23:16] 0x00
0x33 FTW MSB FTW[31:24] 0x00
0x34
NCO phase
offset LSB
NCO Phase Offset[7:0] 0x00
0x35
NCO phase
offset MSB
NCO Phase Offset[15:8] 0x00
0x36
NCO FTW
update
FRAME
FTW ack
FRAME
FTW
request
Update
FTW ack
Update
FTW
request
0x00
0x38 I phase adj LSB I Phase Adj[7:0] 0x00
0x39 I phase adj MSB I Phase Adj[9:8] 0x00
0x3A Q phase adj LSB Q Phase Adj[7:0] 0x00
0x3B Q phase adj MSB Q Phase Adj[9:8] 0x00
0x3C I DAC offset LSB I DAC Offset[7:0] 0x00
0x3D I DAC offset MSB I DAC Offset[15:8] 0x00
0x3E
Q DAC offset
LSB
Q DAC Offset[7:0] 0x00
0x3F
Q DAC offset
MSB
Q DAC Offset[15:8] 0x00
0x40 I DAC FS adjust I DAC FS Adj[7:0] 0xF9
0x41 I DAC control
I DAC
sleep
I DAC FS Adj[9:8] 0x01
0x42 I aux DAC data I Aux DAC[7:0] 0x00
0x43
I aux DAC
control
I aux
DAC sign
I aux DAC
current
direction
I aux DAC
sleep
I Aux DAC[9:8] 0x00
0x44 Q DAC FS adjust Q DAC FS Adj[7:0] 0xF9
0x45 Q DAC control
Q DAC
sleep
Q DAC FS Adj[9:8] 0x01
0x46 Q aux DAC data Q Aux DAC[7:0] 0x00
0x47
Q aux DAC
control
Q aux
DAC sign
Q aux DAC
current
direction
Q aux
DAC
sleep
Q Aux DAC[9:8] 0x00
0x48
Die temp range
control
FS Current[2:0] Reference Current[2:0]
Capacitor
value
0x02
0x49 Die temp LSB Die Temp[7:0] N/A
0x4A Die temp MSB Die Temp[15:8] N/A
0x67 SED control
SED
compare
enable
Sample
error
detected
Autoclear
enable
Compare
fail
Compare
pass
0x00
0x68 Compare I0 LSBs Compare Value I0[7:0] 0xB6
0x69
Compare
I0 MSBs
Compare Value I0[15:8] 0x7A
0x6A
Compare
Q0 LSBs
Compare Value Q0[7:0] 0x45
0x6B
Compare
Q0 MSBs
Compare Value Q0[15:8] 0xEA