Datasheet

AD9122
Rev. B | Page 20 of 60
SERIAL PORT OPTIONS
The serial port can support both MSB first and LSB first data
formats. This functionality is controlled by the LSB_FIRST bit
(Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0).
When LSB_FIRST = 0 (MSB first), the instruction and data bits
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes should follow from high address to low address. In
MSB first mode, the serial port internal byte address generator
decrements for each data byte of the multibyte communication
cycle.
When LSB_FIRST = 1 (LSB first), the instruction and data bits
must be written from LSB to MSB. Multibyte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte. Subsequent
data bytes should follow from low address to high address. In
LSB first mode, the serial port internal byte address generator
increments for each data byte of the multibyte communication
cycle.
If the MSB first mode is active, the serial port controller data
address decrements from the data address written toward 0x00
for multibyte I/O operations. If the LSB first mode is active, the
serial port controller data address increments from the data
address written toward 0x7F for multibyte I/O operations.
R/W A6 A5 A4 A3 A2 A1 A0 D7
N
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
D7
N
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CS
SCLK
SDIO
SDO
08281-011
Figure 39. Serial Port Interface Timing, MSB First
SCLK
SDIO
SDO
CS
A0 A1 A2 A3 A4 A5 A6 D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
INSTRUCTION CYCLE DATA TRANSFER CYCLE
08281-012
R/W
Figure 40. Serial Port Interface Timing, LSB First
SCL
K
SDIO
CS
INSTRUCTION BIT 6INSTRUCTION BIT 7
t
DCSB
t
DS
t
DH
t
PWH
t
PWL
t
SCLK
08281-013
Figure 41. Timing Diagram for Serial Port Register Write
SCL
K
SDIO,
SDO
CS
DATA BIT n – 1DATA BIT n
t
DV
0
8281-014
Figure 42. Timing Diagram for Serial Port Register Read