Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter AD9122 The AD9122 TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters.
AD9122 TABLE OF CONTENTS Features .............................................................................................. 1 Data Rates vs. Interpolation Modes ......................................... 42 Applications ....................................................................................... 1 Coarse Modulation Mixing Sequences.................................... 42 General Description .........................................................................
AD9122 REVISION HISTORY 5/11—Rev. A to Rev. B Change to General Description Section ......................................... 1 Added Companion Products Section ............................................. 1 Moved Power Supply Rejection Ratio Parameter from Power Consumption Section of Table 1 to Main DAC Outputs Section of Table 1............................................................................................. 5 Moved Power-Up Time Parameter from Table 3 to Table 1 ........
AD9122 FUNCTIONAL BLOCK DIAGRAM 16 IOUT1P DAC 1 AUX 16-BIT IOUT1N 16 fDATA /2 PRE MOD NCO AND MOD HB1 HB2 10 HB3 I OFFSET Q OFFSET INV SINC DAC_CLK 16 16 INVSINC_CLK INTP FACTOR HB3_CLK HB2_CLK MODE HB1_CLK FRAME PHASE CORRECTION DCI 10 1.2G IOUT2P DAC 2 AUX 16-BIT IOUT2N GAIN 2 FIFO GAIN 1 DATA RECEIVER D15P/D15N D0P/D0N 1.
AD9122 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Power Supply Rejection Ratio, AVDD33 Output Resistance Gain DAC Monotonicity Settling Time to Within ±0.
AD9122 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2.
AD9122 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4.
AD9122 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6.
AD9122 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 CVDD18 CVDD18 REFCLKP REFCLKN AVDD33 IOUT1P IOUT1N AVDD33 AVSS FSADJ REFIO AVSS AVDD33 IOUT2N IOUT2P AVDD33 AVSS NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9122 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RESET CS SCLK SDIO SDO DVDD18 D0N D0P D1N D1P DVSS DVDD18 D2N D2P D3N D3P D4N D4P NOTES 1.
AD9122 Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Mnemonic D8P D8N DCIP DCIN DVDD18 DVSS D7P D7N D6P D6N D5P D5N D4P D4N D3P D3N D2P D2N DVDD18 DVSS D1P D1N D0P D0N DVDD18 SDO SDIO SCLK CS RESET NC AVSS AVDD33 IOUT2P IOUT2N AVDD33 AVSS REFIO FSADJ AVSS AVDD33 IOUT1N IOUT1P AVDD33 REFCLKN REFCLKP CVDD18 CVDD18 EPAD Description Data Bit 8, Positive. Data Bit 8, Negative. Data Clock Input, Positive.
AD9122 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –20 –30 –40 –50 –60 –70 –50 –60 –70 –90 –100 0 50 100 150 200 250 300 350 400 450 08281-101 –90 –100 0 0 100 150 200 250 300 350 400 450 0dBFS –6dBFS –12dBFS –18dBFS –10 –20 THIRD HARMONIC (dBc) –20 50 fOUT (MHz) fDATA = 100MSPS, SECOND HARMONIC fDATA = 100MSPS, THIRD HARMONIC fDATA = 200MSPS, SECOND HARMONIC fDATA = 200MSPS, THIRD HARMONIC –10 0 Figure 7. Second Harmonic vs.
AD9122 –69 fDATA = 250MSPS fDATA = 400MSPS HIGHEST DIGITAL SPUR (dBc) –70 2× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 250MSPS, fOUT = 101MHz –71 –72 –73 –74 –75 –76 –77 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) Figure 10. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA fDATA = 100MSPS fDATA = 200MSPS STOP 500.0MHz SWEEP 6.
AD9122 –10 –20 –30 –30 IMD (dBc) –20 –40 –50 –40 –50 –60 –60 –70 –70 –80 –80 –90 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) –90 50 100 150 200 250 300 350 400 450 Figure 19. IMD vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, IFS = 20 mA –50 fDATA = 100MSPS fDATA = 200MSPS –10 0 fOUT (MHz) Figure 16. IMD vs.
AD9122 –152 1×, fDATA 2×, fDATA 4×, fDATA 8×, fDATA –154 –161.0 = 200MSPS = 200MSPS = 200MSPS = 100MSPS 1×, fDATA 2×, fDATA 4×, fDATA 8×, fDATA –161.5 –162.0 = 200MSPS = 200MSPS = 200MSPS = 100MSPS –156 NSD (dBm/Hz) NSD (dBm/Hz) –162.5 –158 –160 –163.0 –163.5 –164.0 –162 –164.5 –164 50 100 150 200 250 300 350 400 450 fOUT (MHz) –165.5 –161.0 150 200 250 300 350 400 450 0dBFS –6dBFS –12dBFS –18dBFS –161.5 –162.0 –162.5 NSD (dBm/Hz) –158 NSD (dBm/Hz) 100 Figure 25.
AD9122 –77 –50 0dBFS –3dBFS –6dBFS –78 ACLR (dBc) OFF OFF ON ON –81 –65 –70 –75 –80 –83 –85 50 100 150 200 250 fOUT (MHz) –90 08281-125 0 200 300 400 500 Figure 31. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation, Adjacent Channel, PLL On and PLL Off –70 0dBFS –3dBFS –6dBFS –80 100 fOUT (MHz) Figure 28. One-Carrier W-CDMA ACLR vs.
AD9122 FREQ OFFSET 5.00MHz 10.00MHz 15.00MHz REF BW 3.840MHz 3.840MHz 2.888MHz LOWER dBc dBm –75.96 –85.96 –85.33 –95.33 –95.81 –95.81 UPPER dBc dBm –77.13 –87.13 –85.24 –95.25 –85.43 –95.43 VBW 30kHz STOP 174.42MHz SWEEP 206.9ms (601 PTS) TOTAL CARRIER POWER –11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22 REF CARRIER POWER –16.89dBm/3.84000MHz 1 2 3 4 Figure 34. One-Carrier W-CDMA ACLR Performance, IF = ~150 MHz –16.92dBm –16.89dBm –17.43dBm –17.64dBm OFFSET FREQ 5.000MHz 10.00MHz 15.
AD9122 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition.
AD9122 DIFFERENCES BETWEEN AD9122R1 AND AD9122R2 • • • • IOVDD supply voltage range. For the AD9122R1, the valid operational voltage range for IOVDD is 1.8 V to 2.5 V ± 10%. For the AD9122R2, the valid operational voltage range for IOVDD is 1.8 V to 3.3 V ± 10%. Reduction in spurs level variation. The AD9122R1 has variation in the fDATA ± fOUT spur level between device startups. The AD9122R2 has a consistent and lower fDATA ± fOUT spur level.
AD9122 THEORY OF OPERATION The AD9122 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband (SSB) transmitters. The speed and performance of the AD9122 allow wider bandwidths and more carriers to be synthesized than in previously available DACs.
AD9122 INSTRUCTION CYCLE SERIAL PORT OPTIONS When LSB_FIRST = 1 (LSB first), the instruction and data bits must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte. Subsequent data bytes should follow from low address to high address. In LSB first mode, the serial port internal byte address generator increments for each data byte of the multibyte communication cycle.
AD9122 DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS Table 10.
AD9122 Addr (Hex) 0x1C 0x1D 0x1E 0x1F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 Register Name HB1 control HB2 control HB3 control Chip ID FTW LSB FTW FTW FTW MSB NCO phase offset LSB NCO phase offset MSB NCO FTW update I phase adj LSB I phase adj MSB Q phase adj LSB Q phase adj MSB I DAC offset LSB I DAC offset MSB Q DAC offset LSB Q DAC offset MSB I DAC FS adjust I DAC control 0x42 0x43 I aux DAC data I aux DAC control 0x44 0x45 Q DAC FS adjust Q DAC control
AD9122 Addr (Hex) 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x7F Register Name Compare I1 LSBs Compare I1 MSBs Compare Q1 LSBs Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Revision Bit 7 Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 Compare Value I1[7:0] Compare Value I1[15:8] Bit 1 Bit 0 Default 0x16 0x1A Compare Value Q1[7:0] 0xC6 Compare Value Q1[15:8] 0xAA Errors Detected I_BITS[7:0] Errors Detected I_BITS[15:8] Errors Detected Q_BITS[7:0] Errors Detected Q_BITS[15:8] Revision[3:0] 0x00
AD9122 Register Name Interrupt Enable Address (Hex) 0x05 Event Flag 0x06 Bits [7:5] 4 3 2 [1:0] 7 6 5 4 1 0 0x07 4 3 2 Clock Receiver Control 0x08 7 6 5 4 PLL Control 0x0A 7 6 0x0C [5:0] [7:6] [4:0] Name Set to 0 Enable AED compare pass Enable AED compare fail Enable SED compare fail Set to 0 PLL lock lost Description Set these bits to 0. 1 = enable interrupt for AED comparison pass. 1 = enable interrupt for AED comparison fail. 1 = enable interrupt for SED comparison fail.
AD9122 Register Name PLL Control PLL Status Sync Control Address (Hex) 0x0D Bits [7:6] Name N2[1:0] 4 [3:2] PLL cross-control enable N0[1:0] [1:0] N1[1:0] 0x0E 7 PLL locked 0x0F 0x10 [3:0] [5:0] 7 6 VCO Control Voltage[3:0] VCO Band Readback[5:0] Sync enable Data/FIFO rate toggle 3 Rising edge sync [2:0] Sync Averaging[2:0] [5:0] Sync Phase Request[5:0] 0x11 Description PLL control clock divider.
AD9122 Register Name Sync Status Address (Hex) 0x12 0x13 Data Receiver Status 0x15 Bits 7 6 [7:0] Name Sync lost Sync locked Sync Phase Readback[7:0] 5 4 LVDS FRAME level high LVDS FRAME level low 3 2 LVDS DCI level high LVDS DCI level low LVDS data level high LVDS data level low DCI Delay[1:0] DCI Delay 0x16 1 0 [1:0] FIFO Control 0x17 [2:0] FIFO Phase Offset[2:0] FIFO Status 0x18 7 6 2 1 FIFO Warning 1 FIFO Warning 2 FIFO soft align acknowledge FIFO soft align request [7:0] FIFO Leve
AD9122 Register Name Datapath Control Address (Hex) 0x1B Bits 7 6 5 3 Name Bypass premod Bypass sinc−1 Bypass NCO NCO gain 2 1 Bypass phase compensation and dc offset Select sideband 0 Send I data to Q data HB1 Control 0x1C [2:1] HB1[1:0] HB2 Control 0x1D 0 [6:1] Bypass HB1 HB2[5:0] 0 Bypass HB2 Description 1 = bypass the fS/2 premodulator. 1 = bypass the inverse sinc filter. 1 = bypass the NCO. 0 = no gain scaling is applied to the NCO input to the internal digital modulator (default).
AD9122 Register Name HB3 Control Address (Hex) 0x1E Bits [6:1] Name HB3[5:0] Chip ID FTW LSB FTW FTW FTW MSB 0x1F 0x30 0x31 0x32 0x33 0 [7:0] [7:0] [7:0] [7:0] [7:0] Bypass HB3 Chip ID[7:0] FTW[7:0] FTW[15:8] FTW[23:16] FTW[31:24] NCO Phase Offset LSB NCO Phase Offset MSB 0x34 [7:0] NCO Phase Offset[7:0] 0x35 [7:0] NCO Phase Offset[15:8] NCO FTW Update 0x36 5 FRAME FTW acknowledge 4 FRAME FTW request Update FTW acknowledge Update FTW request I Phase Adj[7:0] I Phase Adj LSB I Phase Adj
AD9122 Register Name Q DAC Offset LSB Q DAC Offset MSB I DAC FS Adjust I DAC Control Address (Hex) 0x3E Bits [7:0] Name Q DAC Offset[7:0] Description See Register 0x3F. Default 00000000 0x3F [7:0] Q DAC Offset[15:8] 00000000 0x40 [7:0] I DAC FS Adj[7:0] Q DAC Offset[15:0] is a value that is added directly to the samples written to the Q DAC. See Register 0x41, Bits[1:0].
AD9122 Register Name Q Aux DAC Control Die Temp Range Control Die Temp LSB Die Temp MSB SED Control Compare I0 LSBs Compare I0 MSBs Compare Q0 LSBs Compare Q0 MSBs Compare I1 LSBs Compare I1 MSBs Address (Hex) 0x47 Bits 7 Name Q aux DAC sign 6 Q aux DAC current direction 5 [1:0] Q aux DAC sleep Q Aux DAC[9:8] [6:4] FS Current[2:0] [3:1] Reference Current[2:0] 0 Capacitor value 0x49 [7:0] Die Temp[7:0] 0x4A [7:0] Die Temp[15:8] 0x67 7 SED compare enable 5 Sample error detected 3
AD9122 Register Name Compare Q1 LSBs Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Revision Address (Hex) 0x6E Bits [7:0] Name Compare Value Q1[7:0] Description See Register 0x6F. Default 11000110 0x6F [7:0] Compare Value Q1[15:8] 10101010 0x70 [7:0] 0x71 [7:0] [7:0] Errors Detected I_BITS[15:0] indicates which bits were received in error. See Register 0x73. 00000000 0x72 0x73 [7:0] [5:2] Errors Detected Q_BITS[15:0] indicates which bits were received in error.
AD9122 LVDS INPUT DATA PORTS The AD9122 has one LVDS data port that receives data for both the I and Q transmit paths. The device can accept data in word, byte, and nibble formats. In word, byte, and nibble modes, the data is sent over 16-bit, 8-bit, and 4-bit LVDS data buses, respectively. The pin assignments of the bus in each mode are shown in Table 12. BYTE INTERFACE MODE In byte mode, the DCI signal is a reference bit used to generate the data sampling clock.
AD9122 The setup (tS) and hold (tH) times, with respect to the edges, are shown in Figure 46. The minimum setup and hold times are shown in Table 13. tDATA FIFO OPERATION The AD9122 contains a 2-channel, 16-bit wide, eight-word deep FIFO designed to relax the timing relationship between the data arriving at the DAC input ports and the internal DAC data rate clock.
AD9122 When the AD9122 is powered on, the FIFO depth is unknown. To avoid a concurrent read and write to the same FIFO address and to ensure a fixed pipeline delay, it is important to reset the FIFO pointers to known states. The FIFO pointers can be initialized in two ways: via a write sequence to the serial port or by strobing the FRAME input. There are two types of FIFO resets: a relative reset and an absolute reset. A relative reset enforces a defined FIFO depth.
AD9122 FRAME Initiated Absolute FIFO Reset Monitoring the FIFO Status In FIFO rate synchronization mode, the write pointer of the FIFO is reset in an absolute manner. The synchronization signal aligns the internal clocks on the part to a common reference clock so that the pipeline delay in the digital circuit stays the same during power cycles. The synchronization signal is sampled by the DAC clock in the AD9122.
AD9122 DIGITAL DATAPATH HB1 HB2 HB3 SINC–1 Figure 50. Block Diagram of Digital Datapath The half-band filters operate in several modes, providing programmable pass-band center frequencies as well as signal modulation. The HB1 filter has four modes of operation, and the HB2 and HB3 filters each have eight modes of operation. Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 51. The shape of the filter response is identical in each of the four modes.
AD9122 Figure 52 shows the pass-band filter response for HB1. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 16 shows the pass-band flatness and stop-band rejection supported by the HB1 filter at different bandwidths. Half-Band Filter 2 (HB2) HB2 has eight modes of operation, as shown in Figure 53 and Figure 54. The shape of the filter response is identical in each of the eight modes.
AD9122 Half-Band Filter 3 (HB3) Table 17 summarizes the HB2 and HB3 modes. HB3 has eight modes of operation that function the same as HB2. The primary difference between HB2 and HB3 is the filter bandwidths. Table 17. HB2 and HB3 Filter Modes fCENTER DC fIN/4 fIN/2 3fIN/4 fIN 5fIN/4 3fIN/2 7fIN/4 fMOD None None None None fIN fIN fIN fIN Input Data Real or complex Complex Complex Complex Real or complex Complex Complex Complex Figure 56 shows the pass-band filter response for HB3.
AD9122 I DATA INTERPOLATION COSINE FTW[31:0] NCO NCO PHASE OFFSET [15:0] OUT_I SINE – OUT_Q + –1 Q DATA 0 1 08281-027 SPECTRAL INVERSION INTERPOLATION Figure 57. Digital Quadrature Modulator Block Diagram NCO MODULATION The digital quadrature modulator makes use of a numerically controlled oscillator (NCO), a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. A block diagram of the digital modulator is shown in Figure 57.
AD9122 The available signal bandwidth for 8× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 59. Note that in 8× interpolation mode, fDAC = 8 × fDATA; therefore, the data shown in Figure 59 repeats eight times from dc to fDAC. HB1, HB2, AND HB3 0.6 Table 20 shows the recommended interpolation filter settings for a variety of filter interpolation factors, filter center frequencies, and signal modulation.
AD9122 DATAPATH CONFIGURATION EXAMPLES 4× Interpolation with NCO 8× Interpolation Without NCO For this example, the following parameters are given: For this example, the following parameters are given: • • • • fDATA = 100 MSPS 8× interpolation fBW = 75 MHz fCENTER = 100 MHz fDATA = 250 MSPS 4× interpolation fBW = 140 MHz fCENTER = 175 MHz The desired 140 MHz of bandwidth is 56% of fDATA. As shown in Figure 58, the value at 0.7 × fDATA is 0.6. This is calculated as 0.8 − 2(0.7 − 0.6) = 0.6.
AD9122 DATA RATES vs. INTERPOLATION MODES Table 22 summarizes the maximum bus speed (fBUS), supported input data rates, and signal bandwidths with the various combinations of bus width modes and interpolation rates. The real signal bandwidth supported is a fraction of the input data rate, which depends on the interpolation filters (HB1, HB2, or HB3) selected. The complex signal bandwidth supported is twice the real signal bandwidth.
AD9122 Q Phase Adj[9:0] (Register 0x3A and Register 0x3B) works in a similar fashion. When Q Phase Adj[9:0] is set to 1000000000, the Q DAC output moves approximately 1.75° away from the I DAC output, creating an angle of 91.75° between the channels. When Q Phase Adj[9:0] is set to 0111111111, the Q DAC output moves approximately 1.75° toward the I DAC output, creating an angle of 88.25° between the channels.
AD9122 DAC INPUT CLOCK CONFIGURATIONS The AD9122 DAC sampling clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying uses the on-chip phase-locked loop (PLL), which accepts a reference clock operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency. The PLL then multiplies the reference clock up to the desired DACCLK frequency, which can then be used to generate all the internal clocks required by the DAC.
AD9122 PLL SETTINGS Manual VCO Band Select Three settings for the PLL circuitry should be programmed to their nominal values. The PLL values shown in Table 23 are the recommended settings for these parameters. The device also has a manual band select mode (PLL manual enable, Register 0x0A, Bit 6 = 1) that allows the user to select the VCO tuning band. In manual mode, the VCO band is set directly with the value written to the manual VCO band bits (Register 0x0A, Bits[5:0]).
AD9122 ANALOG OUTPUTS TRANSMIT DAC OPERATION I DAC FS ADJUST REGISTER 0x40 IOUT1P I DAC REFIO 0.1µF FSADJ 25 10 5 IOUT2N Q DAC Q DAC FS ADJUST REGISTER 0x44 IOUT2P 0 200 400 600 800 1000 Figure 67. DAC Full-Scale Current vs. DAC Gain Code The DAC has a 1.2 V band gap reference with an output impedance of 5 kΩ. The reference output voltage appears on the REFIO pin. When using the internal reference, decouple the REFIO pin to AVSS with a 0.1 μF capacitor.
AD9122 VIP + IOUT1P –60 IFS = 10mA IFS = 20mA IFS = 30mA –65 –70 IMD (dBc) Figure 68 shows the most basic transmit DAC output circuitry. A pair of resistors, RO, is used to convert each of the complementary output currents to a differential voltage output, VOUT. Because the current outputs of the DAC are high impedance, the differential driving point impedance of the DAC outputs, ROUT, is equal to 2 × RO. Figure 69 illustrates the output voltage waveforms.
AD9122 Figure 75 shows a fifth-order, low-pass filter. A common-mode choke is used between the I-V resistors and the remainder of the filter. This removes the common-mode signal produced by the DAC and prevents the common-mode signal from being converted to a differential signal, which can appear as unwanted spurious signals in the output spectrum.
AD9122 REDUCING LO LEAKAGE AND UNWANTED SIDEBANDS Analog quadrature modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs, as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output.
AD9122 DEVICE POWER MANAGEMENT POWER DISSIPATION 1700 The AD9122 has four supply rails: AVDD33, IOVDD, DVDD18, and CVDD18. 1500 1300 POWER (mW) 900 700 500 100 0 50 100 150 200 250 300 fDATA (MHz) 08281-044 300 The IOVDD voltage supplies the serial port I/O pins, the RESET pin, and the IRQ pin. The voltage applied to the IOVDD pin can range from 1.8 V to 3.3 V. The current drawn by the IOVDD supply pin is typically 3 mA. Figure 76. Total Power Dissipation vs.
AD9122 300 TEMPERATURE SENSOR The AD9122 has a band gap temperature sensor for monitoring the temperature change of the AD9122. The temperature must be calibrated against a known temperature to remove the partto-part variation on the band gap circuit used to sense the temperature. The DACCLK must be running at a minimum of 100 MHz to obtain a reliable temperature measurement.
AD9122 MULTICHIP SYNCHRONIZATION Multiple devices are considered synchronized to each other when the state of the clock generation state machines is identical for all parts and when time-aligned data is being read from the FIFOs of all parts simultaneously. Devices are considered synchronized to a system clock when there is a fixed and known relationship between the clock generation state machine and the data being read from the FIFO and a particular clock edge of the system clock.
AD9122 tSKEW REFCLKP(1)/ REFCLKN(1) REFCLKP(2)/ REFCLKN(2) tSDCI tHDCI 08281-050 DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) Figure 82. Timing Diagram Required for Synchronizing Devices SAMPLE RATE CLOCK SYNC CLOCK LOW SKEW CLOCK DRIVER DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN IOUT1P/ IOUT1N MATCHED LENGTH TRACES DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN LOW SKEW CLOCK DRIVER IOUT2P/ IOUT2N 08281-051 FPGA Figure 83.
AD9122 tDATA This completes the synchronization procedure; all devices should now be synchronized. DACCLK/ REFCLK To ensure that each DAC is updated with the correct data on the same CLK edge, two timing relationships must be met on each DAC. • DCIP/DCIN and D[15:0]P/D[15:0]N must meet the setup and hold times with respect to the rising edge of DACCLK. Synchronization (REFCLK) must also meet the setup and hold times with respect to the rising edge of DACCLK.
AD9122 Figure 86 shows the synchronization signal timing with 2× interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is shown to be equal to the FIFO rate. The maximum frequency at which the device can be resynchronized in FIFO rate mode can be expressed as fSYNC_I = fDATA/(8 × 2N) where N is any non-negative integer. Timing Optimization ADDITIONAL SYNCHRONIZATION FEATURES Table 26 shows the required timing between the DACCLK and the synchronization clock when synchronization is used.
AD9122 INTERRUPT REQUEST OPERATION When an interrupt enable bit is set low, the event flag bit reflects the current status of the EVENT_FLAG_SOURCE signal, and the event flag has no effect on the external IRQ pin. The AD9122 provides an interrupt request output signal on Pin 7 (IRQ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred.
AD9122 INTERFACE TIMING VALIDATION The AD9122 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED circuitry compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected and stored.
AD9122 4. SED EXAMPLE Normal Operation 5. The following example illustrates the SED configuration for continuously monitoring the input data and assertion of the IRQ pin when a single error is detected. 1. 2. 3. Load the following comparison values. (Comparison values can be chosen arbitrarily; however, choosing values that require frequent bit toggling provides the most robust test.
AD9122 EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9122, certain sequences should be followed. This section shows an example start-up routine. This example uses the configuration described in the Device Configuration section. Device Configuration Register Write Sequence: DEVICE CONFIGURATION /* Start PLL */ The following device configuration is used for this example: 0x0D Æ 0xD9 • • • • • • • • • • 0x0A Æ 0xC0 fDATA = 122.
AD9122 OUTLINE DIMENSIONS 10.00 BSC SQ 0.60 0.42 0.24 0.60 0.42 0.24 55 54 72 1 PIN 1 INDICATOR PIN 1 INDICATOR 9.75 BSC SQ 0.50 BSC 6.15 6.00 SQ 5.85 EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 37 36 0.80 MAX 0.65 TYP 12° MAX 18 8.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.23 0.18 19 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
