Datasheet

Data Sheet AD9114/AD9115/AD9116/AD9117
Rev. C | Page 7 of 52
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I
xOUTFS
= 20 mA, maximum sample rate, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
DAC CLOCK INPUT (CLKIN)
V
IH
2.1 3 V
V
IL
0 0.9 V
Maximum Clock Rate 125 MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 25 MHz
Minimum Pulse Width High 20 ns
Minimum Pulse Width Low 20 ns
Minimum SDIO and to SCLK Setup, t
DS
10
ns
Minimum SCLK to SDIO Hold, t
DH
5 ns
Maximum SCLK to Valid SDIO, t
DV
20 ns
Minimum SCLK to Invalid SDIO, t
DNV
5 ns
INPUT DATA
1.8 V Q Channel or DCLKIO Falling Edge
Setup 0.25 ns
Hold 1.2 ns
1.8 V I Channel or DCLKIO Rising Edge
Setup 0.13 ns
Hold 1.1 ns
3.3 V Q Channel or DCLKIO Falling Edge
Setup −0.2 ns
Hold 1.5 ns
3.3 V I Channel or DCLKIO Rising Edge
Setup −0.2 ns
Hold 1.6 ns
DVDDIO = 3.3 V
V
IH
2.1 3 V
V
IL
0 0.9 V
DVDDIO = 1.8 V
V
IH
1.2 1.8 V
V
IL
0 0.5 V