Datasheet

AD9114/AD9115/AD9116/AD9117 Data Sheet
Rev. C | Page 12 of 52
PIN 1
INDIC
AT
OR
1
DB7
2
DB6
3DB5
4DB4
5DVDDIO
6DVSS
7
DVDD
8
DB3
9DB2
10DB1
23 QOUTP
24
RLQ
P
25 AVSS
26 A
VDD
27 RLIP
28 IOUTP
29 IOUTN
30 RLIN
22
QOUTN
21
RLQN
11
DB0 (LSB)
12
NC
13
NC
15
NC
17
CVDD
16
DCLKIO
18
CLKIN
19
CVSS
20
CMLQ
14
NC
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMA
T
38
CS/PWRDN
39
DB9 (MSB)
40
DB8
32
FSADJQ/AUXQ
31
CMLI
T
O
P VIEW
(Not to Scale)
AD9115
07466-004
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
MUST BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
Figure 3. AD9115 Pin Configuration
Table 8. AD9115 Pin Function Description
Pin No. Mnemonic Description
1 to 4 DB[7:4] Digital Inputs.
5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS Digital Common.
7 DVDD Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 10 DB[3:1] Digital Inputs.
11
DB0 (LSB)
Digital Input (LSB).
12 to 15 NC No Connect. These pins are not connected to the chip.
16 DCLKIO Data Input/Output Clock. Clock used to qualify input data.
17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18 CLKIN LVCMOS Sampling Clock Input.
19
CVSS
Sampling Clock Supply Voltage Common.
20 CMLQ Q DAC Output Common-Mode Level. When the internal on-chip (QR
CML
) is enabled, this pin is connected to
the on-chip QR
CML
resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QR
CML
) is
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
21 RLQN Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24 RLQP Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25 AVSS Analog Common.
26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30
RLIN
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.