Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LFCSP 40 VQ

Dual Low Power, 8-/10-/12-/14-Bit

TxDAC Digital-to-Analog Converters

Data Sheet

AD9114/AD9115/AD9116/AD9117

Rev. C

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FEATURES

Power dissipation @ 3.3 V, 20 mA output

191 mW @ 10 MSPS

232 mW @ 125 MSPS

Sleep mode: <3 mW @ 3.3 V

Supply voltage: 1.8 V to 3.3 V

SFDR to Nyquist

86 dBc @ 1 MHz output

85 dBc @ 10 MHz output

AD9117 NSD @ 1 MHz output, 125 MSPS, 20 mA: −162 dBc/Hz

Differential current outputs: 2 mA to 20 mA

2 on-chip auxiliary DACs

CMOS inputs with single-port operation

Output common mode: adjustable 0 V to 1.2 V

Small footprint 40-lead LFCSP RoHS-compliant package

APPLICATIONS

Wireless infrastructures

Picocell, femtocell base stations

Medical instrumentation

Ultrasound transducer excitation

Portable instrumentation

Signal generators, arbitrary waveform generators

GENERAL DESCRIPTION

The AD9114/AD9115/AD9116/AD9117 are pin-compatible

dual, 8-/10-/12-/14-bit, low power digital-to-analog converters

(DACs) that provide a sample rate of 125 MSPS. These TxDAC®

converters are optimized for the transmit signal path of commu-

nication systems. All the devices share the same interface, package,

and pinout, providing an upward or downward component

selection path based on performance, resolution, and cost.

The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and

dc performance and support update rates up to 125 MSPS.

The flexible power supply operating range of 1.8 V to 3.3 V and

low power dissipation of the AD9114/AD9115/AD9116/AD9117

make them well suited for portable and low power applications.

PRODUCT HIGHLIGHTS

1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply;

total power consumption reduces to 225 mW at 100 MSPS.

Sleep and power-down modes are provided for low power

idle periods.

2. CMOS Clock Input. High speed, single-ended CMOS clock

input supports a 125 MSPS conversion rate.

3. Easy Interfacing to Other Components. Adjustable output

common mode from 0 V to 1.2 V allows for easy interfacing

to other components that accept common-mode levels

greater than 0 V.

Summary of content (52 pages)

PAGE 1
Data Sheet Dual Low Power, 8-/10-/12-/14-Bit TxDAC Digital-to-Analog Converters AD9114/AD9115/AD9116/AD9117 FEATURES GENERAL DESCRIPTION Power dissipation @ 3.3 V, 20 mA output 191 mW @ 10 MSPS 232 mW @ 125 MSPS Sleep mode: <3 mW @ 3.3 V Supply voltage: 1.8 V to 3.
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AD9114/AD9115/AD9116/AD9117 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Descriptions .............................................................. 36 Applications ....................................................................................... 1 Digital Interface Operation ........................................................... 40 General Description .....................................
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Data Sheet AD9114/AD9115/AD9116/AD9117 REVISION HISTORY 3/13—Rev. B to Rev. C Change to Features Section .............................................................. 1 Change to Endnote 1, Table 1 .......................................................... 6 Changes to Figure 86 and Figure 88 .............................................34 Change to Table 13 ..........................................................................35 Change to Version Register Description, Table 14 .....................
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AD9114/AD9115/AD9116/AD9117 Data Sheet AD9117 1V SPI INTERFACE DB11 CMLI FSADJI/AUXI FSADJQ/AUXQ REFIO RESET/PINMD SCLK/CLKMD SDIO/FORMAT CS/PWRDN DB13 (MSB) DB12 FUNCTIONAL BLOCK DIAGRAM QRSET 2kΩ IRSET 2kΩ DB10 10kΩ DB9 RLIN 62.5Ω IOUTN IREF 100µA DB8 I DAC IOUTP 62.5Ω BAND GAP DVDDIO RLIP AUX1DAC AVDD 1 INTO 2 INTERLEAVED DATA INTERFACE DVSS DVDD IRCM 60Ω TO 260Ω AVSS AUX2DAC I DATA RLQP 62.5Ω 1.8V LDO QOUTP Q DATA Q DAC QOUTN DB7 62.5Ω Figure 1. Rev.
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Data Sheet AD9114/AD9115/AD9116/AD9117 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY, AVDD = DVDDIO = CVDD = 3.3 V Differential Nonlinearity (DNL) Precalibration Postcalibration Integral Nonlinearity (INL) Precalibration Postcalibration ACCURACY, AVDD = DVDDIO =CVDD = 1.
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AD9114/AD9115/AD9116/AD9117 Parameter AUXDAC OUTPUTS Resolution Full-Scale Output Current (Current Sourcing Mode) Voltage Output Mode Output Compliance Range (Sourcing 1 mA) Output Compliance Range (Sinking 1 mA) Output Resistance in Current Output Mode AVSS to 1 V AUXDAC Monotonicity Guaranteed REFERENCE OUTPUT Internal Reference Voltage Output Resistance REFERENCE INPUT Voltage Compliance AVDD = 3.3 V AVDD = 1.
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Data Sheet AD9114/AD9115/AD9116/AD9117 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2.
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AD9114/AD9115/AD9116/AD9117 Data Sheet AC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Output Settling Time (tST) to 0.
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Data Sheet AD9114/AD9115/AD9116/AD9117 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS DVDD to DVSS AVSS to DVSS, CVSS DVSS to AVSS, CVSS CVSS to AVSS, DVSS REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, RLIP, RLIN to AVSS DBn1 (MSB) to D0 (LSB), CS, SCLK, SDIO, RESET to DVSS CLKIN to CVSS Junction Temperature Storage Temperature Range 1 THERMAL RESISTANCE Rating −0.3 V to +3.9 V Table 6.
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AD9114/AD9115/AD9116/AD9117 Data Sheet 40 39 38 37 36 35 34 33 32 31 DB6 DB7 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AD9114 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND MUST BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
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Data Sheet Pin No. 29 30 Mnemonic IOUTN RLIN 31 CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 DB7 (MSB) DB6 EP (EPAD) AD9114/AD9115/AD9116/AD9117 Description Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. I DAC Output Common-Mode Level.
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Data Sheet 40 39 38 37 36 35 34 33 32 31 DB8 DB9 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI AD9114/AD9115/AD9116/AD9117 PIN 1 INDICATOR AD9115 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND MUST BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
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Data Sheet Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 DB9 (MSB) DB82 EP (EPAD) AD9114/AD9115/AD9116/AD9117 Description I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected.
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Data Sheet 40 39 38 37 36 35 34 33 32 31 DB10 DB11 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI AD9114/AD9115/AD9116/AD9117 PIN 1 INDICATOR AD9116 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND MUST BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
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Data Sheet Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 DB11 (MSB) DB10 EP (EPAD) AD9114/AD9115/AD9116/AD9117 Description I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected.
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Data Sheet 40 39 38 37 36 35 34 33 32 31 DB12 DB13 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI AD9114/AD9115/AD9116/AD9117 PIN 1 INDICATOR AD9117 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. THE EXPOSED PAD IS CONNECTED TO AVSS AND MUST BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
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Data Sheet Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 DB13 (MSB) DB12 EP (EPAD) AD9114/AD9115/AD9116/AD9117 Description I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected.
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AD9114/AD9115/AD9116/AD9117 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 1.5 1.5 POSTCALIBRATION INL (LSB) 1.0 0.5 0 –0.5 –1.0 0 –0.5 –1.0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE –2.0 0 Figure 6. AD9117 Precalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V) 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE 07466-009 0 07466-006 –2.0 Figure 9. AD9117 Postcalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V) 2.0 2.0 1.5 1.5 POSTCALIBRATION DNL (LSB) 1.0 0.5 0 –0.5 –1.
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AD9114/AD9115/AD9116/AD9117 1.5 1.5 1.0 1.0 POSTCALIBRATION DNL (LSB) 0.5 0 –0.5 –1.0 0.5 0 –0.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE –1.5 07466-012 –1.5 0 0.8 0.8 0.6 0.6 0.4 0.2 0 –0.2 –0.4 6144 8192 10,240 12,288 14,336 16,384 CODE 0.4 0.2 0 –0.2 –0.4 –0.6 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 –0.8 07466-013 –0.8 0 Figure 13. AD9116 Precalibration INL at 1.8 V, 8 mA 512 1024 1536 2048 CODE 2560 3072 3584 4096 07466-016 –0.
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Data Sheet 0.8 0.8 0.6 0.6 POSTCALIBRATION INL (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 0.4 0.2 0 –0.2 –0.4 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 –0.8 07466-018 –0.8 0 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 1536 2048 CODE 2560 3072 3584 4096 0.2 0.1 0 –0.1 –0.2 –0.3 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 –0.5 07466-019 –0.5 0 Figure 19. AD9116 Precalibration DNL at 3.3 V, 20 mA 512 1024 1536 2048 CODE 2560 3072 3584 4096 07466-022 –0.
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AD9114/AD9115/AD9116/AD9117 0.08 0.08 0.06 0.06 POSTCALIBRATION DNL (LSB) 0.04 0.02 0 –0.02 –0.04 –0.06 0.04 0.02 0 –0.02 –0.04 0 128 256 384 512 CODE 640 768 896 1024 –0.08 07466-024 –0.08 0 Figure 24. AD9115 Precalibration DNL at 1.8 V, 8 mA 384 512 CODE 640 768 896 1024 0.25 0.20 0.20 0.15 0.15 POSTCALIBRATION INL (LSB) 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0 128 256 384 512 CODE 640 768 896 1024 –0.25 07466-025 –0.
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Data Sheet 0.035 0.035 0.025 0.025 POSTCALIBRATION INL (LSB) 0.015 0.005 0 –0.005 –0.015 –0.025 0.015 0.005 0 –0.005 –0.015 0 32 64 96 128 CODE 160 192 224 256 –0.035 07466-030 –0.035 0 0.025 0.025 0.020 0.020 0.015 0.015 0.010 0.005 0 –0.005 –0.010 –0.015 96 128 CODE 160 192 224 256 0.010 0.005 0 –0.005 –0.010 –0.015 0 32 64 96 128 CODE 160 192 224 256 –0.025 07466-031 –0.025 0 Figure 31. AD9114 Precalibration DNL at 1.
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AD9114/AD9115/AD9116/AD9117 0.025 0.025 0.020 0.020 0.015 0.015 POSTCALIBRATION DNL (LSB) 0.010 0.005 0 –0.005 –0.010 –0.015 0.010 0.005 0 –0.005 –0.010 –0.015 –0.020 –0.020 64 32 0 96 128 CODE 160 192 224 256 –0.025 07466-036 –0.025 0 32 64 96 128 160 192 224 256 CODE Figure 36. AD9114 Precalibration DNL at 3.3 V, 20 mA 07466-039 PRECALIBRATION DNL (LSB) Data Sheet Figure 39. AD9114 Postcalibration DNL at 3.
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AD9114/AD9115/AD9116/AD9117 Data Sheet –130 –130 –136 1.8V, 8mA –142 NSD (dBc) –142 NSD (dBc) –136 1.8V, 4mA –148 –148 –154 –154 –160 –160 3.3V, 4mA 3.3V, 8mA 3.3V, 20mA 10 15 20 25 30 fOUT (MHz) 35 40 45 50 55 –166 0 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –70 –70 –80 –80 –90 –90 1.5MHz/DIV STOP 16MHz 07466-090 –60 START 1MHz 20 25 30 fOUT (MHz) 35 40 45 50 55 –100 1.5MHz/DIV START 1MHz Figure 43. AD9117 Two Tone Spectrum at 1.
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Data Sheet AD9114/AD9115/AD9116/AD9117 84 90 87 78 84 81 IMD (dBc) IMD (dBc) 72 66 –40°C 60 78 75 –40°C 72 +25°C +25°C 69 54 15 20 25 30 35 40 45 50 63 fOUT (MHz) 5 10 15 20 25 30 35 40 45 07466-196 10 07466-195 48 5 +85°C 66 +85°C 50 fOUT (MHz) Figure 48. AD9117 IMD at Three Temperatures 8 mA vs. fOUT, 1.8 V Figure 51. AD9117 IMD at Three Temperatures 20 mA vs. fOUT, 3.
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AD9114/AD9115/AD9116/AD9117 Data Sheet 0 0 –10 –10 –20 –20 –30 –30 –40 (dBm) –50 –50 –60 –60 –70 –70 –80 –90 –90 07466-088 –80 –100 START 1MHz 1.5MHz/DIV STOP 16MHz 07466-089 (dBm) –40 –100 START 1MHz Figure 54. AD9117 Singe Tone Spectrum, 1.8 V 1.5MHz/DIV STOP 16MHz Figure 57. AD9117 Singe Tone Spectrum, 3.
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Data Sheet AD9114/AD9115/AD9116/AD9117 98 98 90 90 82 SFDR (dBc) 74 66 74 66 58 –6dB –6dB –3dB 50 –3dB 58 5 10 15 20 25 30 35 40 45 50 55 60 50 fOUT (MHz) 0 5 10 96 90 90 84 84 8mA SFDR (dBc) 8mA 54 54 0 10 20 30 40 50 40 45 50 55 60 20mA 66 60 42 35 72 60 48 30 4mA 78 07466-161 SFDR (dBc) 78 66 25 Figure 63. AD9117 SFDR at Three Digital Signal Levels vs. fOUT., 3.3 V 96 72 20 fOUT (MHz) Figure 60.
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AD9114/AD9115/AD9116/AD9117 Data Sheet –60 –60 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL 16mA PRECAL 16mA POSTCAL –66 ACLR (dBc) ACLR (dBc) –66 –72 15 20 25 30 35 40 45 fOUT (MHz) –78 15 20 25 30 35 40 45 fOUT (MHz) Figure 66. AD9117 One-Carrier W-CDMA First ACLR vs. fOUT, 1.8 V 07466-169 –78 07466-166 –72 Figure 69. AD9117 One-Carrier W-CDMA First ACLR vs. fOUT, 3.
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Data Sheet AD9114/AD9115/AD9116/AD9117 AC COUPLED: UNSPECIFIED BELOW 20MHz 10dB/DIV INPUT ATT 8.00dB INPUT ATT 8.00dB STEP 2dB STEP 2dB CENTER 22.90MHz SPAN 38.84MHz VBW 300kHz RES BW 30kHz CENTER 22.90MHz SPAN 38.84MHz VBW 300kHz RES BW 30kHz SWEEP 126ms (601pts) SWEEP 126ms (601pts) TOTAL CARRIER POWER –15.23dBm/7.87420MHz REF CARRIER POWER –18.09dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 TOTAL CARRIER POWER –15.23dBm/7.87420MHz REF CARRIER POWER –18.09dBm/4.
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AD9114/AD9115/AD9116/AD9117 Data Sheet –50 –50 4mA PRECAL 4mA POSTCAL 8mA PRECAL 8mA POSTCAL –56 ACLR (dBc) –62 –62 –68 –68 25 30 fOUT (MHz) 40 35 –74 20 30 35 40 fOUT (MHz) Figure 78. AD9117 Two-Carrier W-CDMA Third ACLR vs. fOUT, 1.8 V Figure 81. AD9117 Two-Carrier W-CDMA Third ACLR vs. fOUT, 3.3 V 0.4 1.0 0.3 0.8 0.6 AUXDAC INL (LSB) 0.2 AUXDAC DNL (LSB) 25 07466-181 20 07466-178 –74 0.1 0 –0.1 –0.2 –0.3 0.4 0.2 0 –0.2 –0.4 –0.6 –0.4 –0.
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Data Sheet AD9114/AD9115/AD9116/AD9117 TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.
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AD9114/AD9115/AD9116/AD9117 Data Sheet CMLI FSADJI/AUXI FSADJQ/AUXQ REFIO RESET/PINMD SCLK/CLKMD SDIO/FORMAT CS/PWRDN DB13 (MSB) DB12 THEORY OF OPERATION 1V SPI INTERFACE DB11 AD9117 QRSET 2kΩ IRSET 2kΩ DB10 10kΩ DB9 RLIN 62.5Ω IOUTN IREF 100µA DB8 I DAC IOUTP 62.5Ω BAND GAP DVDDIO RLIP AUX1DAC AVDD 1 INTO 2 INTERLEAVED DATA INTERFACE DVSS DVDD IRCM 60Ω TO 260Ω AVSS AUX2DAC I DATA RLQP 62.5Ω 1.8V LDO QOUTP Q DATA Q DAC QOUTN DB7 62.
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Data Sheet AD9114/AD9115/AD9116/AD9117 SERIAL PERIPHERAL INTERFACE (SPI) The serial port of the AD9114/AD9115/AD9116/AD9117 is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9114/AD9115/AD9116/AD9117.
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AD9114/AD9115/AD9116/AD9117 Data Sheet INSTRUCTION CYCLE MSB/LSB TRANSFERS When LSBFIRST = 1 (LSB first), the instruction and data bytes must be written from the least significant bit to the most significant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle.
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Data Sheet AD9114/AD9115/AD9116/AD9117 SPI REGISTER MAP Table 13.
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AD9114/AD9115/AD9116/AD9117 Data Sheet SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14.
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Data Sheet Register IRSET IRCML AD9114/AD9115/AD9116/AD9117 Address 0x04 0x05 Bit 7 Name IRSETEN 5:0 IRSET[5:0] 7 IRCMLEN 5:0 IRCML[5:0] Q DAC Gain 0x06 5:0 Q DACGAIN[5:0] QRSET 0x07 7 QRSETEN 5:0 QRSET[5:0] 7 QRCMLEN 5:0 QRCML[5:0] QRCML 0x08 AUXDAC Q 0x09 7:0 QAUXDAC[7:0] AUX CTLQ 0x0A 7 QAUXEN 6:5 QAUXRNG[1:0] 4:2 QAUXOFS[2:0] 1:0 QAUXDAC[9:8] Description 0 (default): IRSET resistor value for I channel is set by an external resistor connected to the FADJI/AUXI pi
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AD9114/AD9115/AD9116/AD9117 Register AUXDAC I Address 0x0B Bit 7:0 Name IAUXDAC[7:0] AUX CTLI 0x0C 7 IAUXEN 6:5 IAUXRNG[1:0] 4:2 IAUXOFS[2:0] Reference Resistor 0x0D 1:0 5:0 IAUXDAC[9:8] RREF[5:0] Cal Control 0x0E 7 PRELDQ 6 PRELDI 5 CALSELQ 4 CALSELI 3 CALCLK 2:0 DIVSEL[2:0] 7 CALSTATQ 6 CALSTATI 3:2 CALMEMQ[1:0] 1:0 CALMEMI[1:0] 5:0 5:0 MEMADDR[5:0] MEMDATA[5:0] Cal Memory Memory Address Memory Data 0x0F 0x10 0x11 Data Sheet Description AUXDAC I output voltage a
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Data Sheet Register Memory R/W CLKMODE Version AD9114/AD9115/AD9116/AD9117 Address 0x12 0x14 0x1F Bit 7 Name CALRSTQ 6 CALRSTI 4 CALEN 3 SMEMWR 2 SMEMRD 1 UNCALQ 0 UNCALI 7:6 CLKMODEQ[1:0] 4 Searching 3 2 Reacquire CLKMODEN 1:0 CLKMODEI[1:0] 7:0 Version[7:0] Description 0 (default): no action. 1: clears CALSTATQ. 0 (default): no action. 1: clears CALSTATI. 0 (default): no action. 1: initiates device self-calibration. 0 (default): no action.
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AD9114/AD9115/AD9116/AD9117 Data Sheet DIGITAL INTERFACE OPERATION DCLKIO DB[n:0] Z A B C D E I DATA Z B Q DATA A C F G H D F E G 07466-053 Digital data for the I and Q DACs is supplied over a single parallel bus (DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115, is 11 for the AD9116, and 13 for the AD9117) accompanied by a qualifying clock (DCLKIO). The I and Q data are provided to the chip in an interleaved double data rate (DDR) format.
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Data Sheet AD9114/AD9115/AD9116/AD9117 OR DB[n:0] (INPUT) RETIMER-CLK D-FF D-FF D-FF D-FF 0 1 2 3 D-FF TO DAC CORE IOUT CLKIN-INT IOUT NOTES D-FFs: 0: RISING OR FALLING EDGE TRIGGERED FOR I OR Q DATA. 1, 2, 3, 4: RISING EDGE TRIGGERED. DELAY1 DELAY1 RETIMER-CLK DCLKIO-INT 4 IE IE OE DCLKIO (INPUT/OUTPUT) 07466-056 DELAY2 CLKIN (INPUT) NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117. Figure 94.
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AD9114/AD9115/AD9116/AD9117 Data Sheet Table 15. Timer Register List Bit Name CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Description Q datapath retimer clock selected output. Valid after the searching bit goes low. High indicates that the internal datapath retimer is searching for the clock relationship (DAC is not usable until it is low again). Changing this bit from 0 to 1 causes the datapath retimer circuit to reacquire the clock relationship.
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Data Sheet AD9114/AD9115/AD9116/AD9117 REFERENCE OPERATION REFERENCE CONTROL AMPLIFIER The AD9114/AD9115/AD9116/AD9117 contains an internal 1.0 V band gap reference. The internal reference can be disabled by setting Bit 0 (EXTREF) of the power-down register (Address 0x01) through the SPI interface. To use the internal reference, decouple the REFIO pin to AVSS with a 0.1 μF capacitor, enable the internal reference, and clear Bit 0 of the power-down register (Address 0x01) through the SPI interface.
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AD9114/AD9115/AD9116/AD9117 or Data Sheet where: IIREF = VREFIO/IRSET IQREF = VREFIO/QRSET (4) IIOUTFS = 32 × VREFIO/IRSET (5) IQOUTFS = 32 × VREFIO/QRSET A differential pair (IOUTP/IOUTN or QOUTP/QOUTN) typically drives a resistive load directly or via a transformer. If dc coupling is required, the differential pair (IOUTP/IOUTN or QOUTP/QOUTN) should be connected to matching resistive loads, xRLOAD, that are tied to analog common, AVSS.
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Data Sheet 7. effect to changing the REFIO voltage is that the full-scale voltage in the AUXDAC also changes by the same magnitude. The register uses twos complement format, in which 011111 maximizes the voltage on the REFIO node and 100000 minimizes the voltage. 1.30 1.25 1.20 The AD9114/AD9115/AD9116/AD9117 allow reading and writing of the calibration coefficients. There are 32 coefficients in total.
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AD9114/AD9115/AD9116/AD9117 Data Sheet REFIO pin. Noise injected here appears as amplitude modulation of the output; therefore, a portion of the required series resistance (at least 10 kΩ) must be installed at the pin. A range of ±25% is quite practical when using this method. CML xRCM 11.10 3.3V DAC1 3.3V DAC2 1.8V DAC1 1.8V DAC2 11.00 IOUTP 07466-061 62.5Ω RLIP Figure 100.
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Data Sheet AD9114/AD9115/AD9116/AD9117 APPLICATIONS INFORMATION OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9114/AD9115/AD9116/AD9117. Unless otherwise noted, it is assumed that IxOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration.
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AD9114/AD9115/AD9116/AD9117 Data Sheet DIFFERENTIAL BUFFERED OUTPUT USING AN OP AMP A dual op amp (see the circuit shown in Figure 104) can be used in a differential version of the single-ended buffer shown in Figure 103. Figure 104 is a simplified schematic. The REFIO pin must be buffered to keep the load current less than 100 nA. The same RC network is used to form a one-pole differential, low-pass filter to isolate the op amp inputs from the high frequency images produced by the DAC outputs.
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AD9114/AD9115/AD9116/AD9117 Two registers are assigned to each DAC with 10 bits for the actual DAC current to be generated, a 3-bit offset (and gain) adjustment, a 2-bit current range adjustment, and an enable/ disable bit. Setting the QAUXOFS (Register 0x0A) and IAUXOFS (Register 0x0C) bits to all 1s disables the respective op amp and routes the DAC current directly to the respective FSADJI/AUXI or FSADJQ/AUXQ pins.
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AD9114/AD9115/AD9116/AD9117 Data Sheet To achieve LO feedthrough compensation, the user should start with the default conditions of the AUXDAC registers and then increment the magnitude of one or the other AUXDAC output voltages. While this is being done, the amplitude of the LO feedthrough at the quadrature modulator output should be sensed.
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Data Sheet AD9114/AD9115/AD9116/AD9117 OUTLINE DIMENSIONS 6.10 6.00 SQ 5.90 0.60 MAX 0.60 MAX PIN 1 INDICATOR 31 30 0.50 BSC 10 21 20 TOP VIEW 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.50 0.40 0.30 11 0.20 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.30 0.23 0.18 4.25 4.10 SQ 3.95 EXPOSED PAD (BOTTOM VIEW) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 06-01-2012-D 5.85 5.
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AD9114/AD9115/AD9116/AD9117 Data Sheet ORDERING GUIDE Model 1 AD9114BCPZ AD9114BCPZRL7 AD9115BCPZ AD9115BCPZRL7 AD9116BCPZ AD9116BCPZRL7 AD9117BCPZ AD9117BCPZRL7 AD9117BCPZN AD9117BCPZNRL7 AD9114-DPG2-EBZ AD9115-DPG2-EBZ AD9116-DPG2-EBZ AD9117-DPG2-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_