Datasheet

REV. A–4–
AD9059
NN + 3N + 5
N + 1
N + 2
N + 4
t
A
t
V
t
PD
t
EH
t
EL
N – 3 N – 2 N – 1 N N + 1 N + 2
ENCODE
AIN
DIGITAL
OUTPUTS
APERTURE DELAY
PULSEWIDTH HIGH
PULSEWIDTH LOW
OUTPUT VALID TIME
OUTPUT PROP DELAY
6.7ns
6.7ns
4.0ns
166ns
166ns
14.2ns
MIN TYP
MAX
9.5ns
6.6n
2.7ns
t
A
t
EH
t
EL
t
V
t
PD
Figure 1. Timing Diagram
PIN CONFIGURATION
14
13
12
11
10
17
16
15
19
18
20
28
27
26
25
24
23
22
21
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD9059
AINA
V
D
ENCODE
GND
AINB
VREF
PWRDN
V
D
D7B (MSB)
V
DD
GND
GND
V
DD
D7A (MSB)
D6A
D5A
D4A
D4B
D5B
D6B
D3A
D2A
D1A
D0A (LSB)
D3B
D0B (LSB)
D1B
D2B
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1, 28 AINA, AINB Analog Inputs for ADC A and B.
2 VREF Internal Voltage Reference (2.5 V
Typical); Bypass with 0.1 µF to
Ground or Overdrive with External
Voltage Reference.
3 PWRDN Power-Down Function Select; Logic
HIGH for Power-Down Mode
(Digital Outputs Go to High-
Impedance State).
4, 25 V
D
Analog 5 V Power Supply.
5, 24, 27 GND Ground.
6, 23 V
DD
Digital Output Power Supply.
Nominally 3 V to 5 V.
7–14 D7A–D0A Digital Outputs of ADC A.
22–15 D7B–D0B Digital Outputs of ADC B.
26 ENCODE Encode Clock for ADCs A and B
(ADCs Sample Simultaneously on
the Rising Edge of ENCODE).
Table I. Digital Coding (VREF = 2.5 V)
Analog Input (V) Voltage Level Digital Output
3.0 Positive Full Scale 1111 1111
2.502 Midscale + 1/2 LSB 1000 0000
2.498 Midscale – 1/2 LSB 0111 1111
2.0 Negative Full Scale 0000 0000