Datasheet

AD8842
REV. –7–
10
90
100
0%
2V
5µs
5µS
5µs
10
90
100
0%
2V
5µs
Figure 13. Pulse Response—Upper Trace V
IN
@ 2 V/Div
Lower Trace V
OUT
@2 V/Div
Figure 16. Settling Time—Upper Trace LD @ 5 V/Div,
Lower Trace V
OUT
@ 2 V/Div
Figure 17. Digital Feedthrough—V
OUT
@ 10 mV/Div,
V
IN
= 0 V; Code 7F
H
to 80
H
10
90
100
0%
2V
5µs
5µS
5µs
10
90
100
0%
5mV
5V
50ns
10
90
100
0%
5mV
2µs
Figure 15. Crosstalk—V
OUT
@ 5 mV/Div Figure 18. Clock Feedthrough—V
OUT
@ 5 mV/Div
Figure 14. Worst Case 1 LSB Step Change Code 80
H
to 7F
H
,
Upper Trace LD @ 5 V/Div, Lower Trace V
OUT
@ 50 mV/Div
10
90
100
0%
2V
5µs
5V
10
90
100
0%
2V
5µs
5µS
5µs
10
90
100
0%
500ns
50mV
5V
10
90
100
0%
50ns
10mV
A